Journal ArticleDOI
Effects of Hafnium Oxide on Surface Potential and Drain Current Models for Subthreshold Short Channel Metal–Oxide–Semiconductor-Field-Effect-Transistor
Niladri Pratap Maity,Reshmi Maity,Subir Dutta,Subhasish Deb,K. Girija Sravani,K. Srinivasa Rao,Srimanta Baishya +6 more
TLDR
In this article, surface potential and drain current models for a physically based double halo metal-oxide-semiconductor-field effect transistor (MOSFET) are reported, where the conventional silicon-dioxide (SiO2) material is replaced with a promising high-k dielectric material hafnium oxide (HfO2).Abstract:
Surface potential and drain current models for a physically based double halo metal–oxide–semiconductor-field-effect-transistor (MOSFET) are reported. The proposed models have been established in sub-threshold mode of MOSFET operation. The depletion layer depth used in the pseudo two dimensional Poisson’s equation comprises the effect of two symmetrical pocket implantations at both the ends of the channel region. In this effort, improvement in the investigation is brought in by taking lateral asymmetric channel owing to non-uniform doping. The conventional silicon-dioxide (SiO2) material is replaced with a promising high-k dielectric material hafnium oxide (HfO2) to analyze the surface potential and drain current models. Analytical results have been compared using Synopsys technology computer aided design (TCAD). Excellent conformities between the analytical models and simulations are observed.read more
Citations
More filters
Journal ArticleDOI
Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET
TL;DR: An analytical model for surface potential and threshold voltage for undoped (or lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated using transistor computer aided design (TCAD) simulation.
Journal ArticleDOI
An Accurate Model for Threshold Voltage Analysis of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor
TL;DR: In this paper, an accurate representation of threshold voltage for double metal double gate (DMDG) device structure has been initiated, which is the lowest gate-source electromotive force at which the device can kick off to conduct.
Journal ArticleDOI
Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET
TL;DR: In this paper, a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET is presented.
Journal ArticleDOI
An Insight into the DC and Analog/RF Response of a Junctionless Vertical Super-Thin Body FET towards High-K Gate Dielectrics
TL;DR: In this article, the junctionless (JL) feature is incorporated in a newly invented device called vertical super-thin body (VSTB) FET and a comparative exploration of DC and analog/RF figures of merit (FoM) is reported for various gate dielectric materials with high-k (Si3N4/HfO2) and low-k(SiO2), through a properly calibrated Sentaurus TCAD tool.
References
More filters
Journal ArticleDOI
CMOS scaling into the nanometer regime
Yuan Taur,Douglas A. Buchanan,Wei Chen,David J. Frank,Khalid EzzEldin Ismail,Shih-Hsien Lo,George Anthony Sai-Halasz,R. Viswanathan,Hsing-Jen Wann,Shalom J. Wind,Hon-Sum Philip Wong +10 more
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Journal ArticleDOI
A 180-mV subthreshold FFT processor using a minimum energy design methodology
TL;DR: New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor that is designed to investigate the estimated minimum energy point.
Journal ArticleDOI
Threshold voltage model for deep-submicrometer MOSFETs
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Journal ArticleDOI
PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation
G. Gildenblat,Xin Li,W. Wu,H. Wang,Amit Jha,R. van Langevelde,G.D.J. Smit,A.J. Scholten,D.B.M. Klaassen +8 more
TL;DR: In this paper, the authors describe the latest and most advanced surface potential-based model jointly developed by The Pennsylvania State University and Philips, which includes model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources.
Journal ArticleDOI
Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
TL;DR: In this article, the authors analyzed SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, VDD, temperature, and local and global threshold variation.