Introduction to VLSI Systems: A Logic, Circuit, and System Perspective

TLDR: This paper discusses the design and Fabrication options for implementation of VLSI Testing Fault Models, and the design methods used for Verilog HDL/SystemVerilog and Sequential Logic Modules, and their applications.

Abstract: Introduction MOS Transistors as Switches VLSI Design and Fabrication Implementation Options of Digital Systems Fundamentals of MOS Transistors Semiconductor Fundamentals The pn Junction MOS Transistor Theory Advanced Features of MOS Transistors SPICE and Modeling Fabrication of CMOS ICs Basic Processes Materials and Their Applications Process Integration Enhancements of CMOS Processes and Devices Layout Designs Layout Design Rules CMOS Latch-Up and Prevention Layout Designs Layout Methods for Complex Logic Gates Delay Models and Path-Delay Optimization Resistance and Capacitance of MOS Transistors Propagation Delays and Delay Models Path-Delay Optimization Power Dissipation and Low-Power Designs Power Dissipation Principles of Low-Power Logic Designs Low-Power Logic Architectures Power Management Static Logic Circuits Basic Static Logic Circuits Single-Rail Logic Circuits Dual-Rail Logic Circuits Dynamic Logic Circuits Introduction to Dynamic Logic Nonideal Effects of Dynamic Logic Single-Rail Dynamic Logic Dual-Rail Dynamic Logic Clocked CMOS Logic Sequential Logic Designs Sequential Logic Fundamentals Memory Elements Timing Issues in Clocked Systems Pipeline Systems Datapath Subsystem Designs Basic Combinational Components Basic Sequential Components Shifters Addition/Subtraction Multiplication Division Memory Subsystems Introduction Static Random-Access Memory Dynamic Random-Access Memory Read-Only Memory Nonvolatile Memory Other Memory Devices Design Methodologies and Implementation Options Design Methodologies and Implementation Architectures Synthesis Flows Implementation Options of Digital Systems A Case Study | A Simple Start/Stop Timer Interconnect RLC Parasitics Interconnect and Simulation Models Parasitic Effects of Interconnect Transmission-Line Models Advanced Topics Power Distribution and Clock Designs Power Distribution Networks Clock Generation and Distribution Networks Phase-Locked Loops/Delay-Locked Loops Input/Output Modules and ESD Protection Networks General Chip Organizations Output Drivers/Buffers Electrostatic Discharge Protection Networks Testing, Verification, and Testable Designs An Overview of VLSI Testing Fault Models Automatic Test Pattern Generation Testable Circuit Designs System-Level Testing An Introduction to Verilog HDL/SystemVerilog Introduction Behavioral Modeling Hierarchical Structural Modeling Combinational Logic Modules Sequential Logic Modules Synthesis Verification A Start/Stop Timer Index