Proceedings ArticleDOI
Measuring threshold voltage variability of 10G transistors
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TLDR
In this article, the authors measured the threshold voltage variability of 10G transistors using a special device-matrix array test element group (DMA TEG) exclusively for ultra-fast V TH measurements.Abstract:
Threshold voltage (V TH ) variability of 10G (10 billion) transistors is measured using a special device-matrix-array test-element-group (DMA TEG) exclusively for ultra-fast V TH measurements. It is found that V TH variability in nFETs almost follows the normal distribution up to ±6σ, while pFETs have a clear “tail” in low V TH region. The origin of the non-normal distribution is analyzed by measuring transistors fabricated in two different fabs and by 3D device simulation.read more
Citations
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Journal ArticleDOI
Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits
Pieter Weckx,Ben Kaczer,Maria Toledano-Luque,Praveen Raghavan,Jacopo Franco,Philippe Roussel,Guido Groeseneken,Francky Catthoor +7 more
TL;DR: In this article, the impact of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits is discussed, and the statistical distributions encompassing both time-zero and timedependent variability and their correlations are discussed.
Journal ArticleDOI
Methodology for Determination of Process Induced BTI Variability in MG/HK CMOS Technologies Using a Novel Matrix Test Structure
TL;DR: In this paper, a novel transistor test structure utilizing a matrix configuration is introduced to decouple the process variation from the random stochastic variations, and it is shown that the local bias temperature instability (BTI)-induced variance scales inversely with the gate oxide area over a range of 1000x, whereas process variations lead to saturation in the variance when determined using samples across the wafer.
Journal ArticleDOI
A Compact Test Structure for Characterizing Transistor Variability Beyond $3\sigma $
Christopher Chen,Liping Li,Queennie Lim,Hong HaiTeh,Hong Hai Teh,Noor Fadillah Binti Omar,Chun-Lee Ler,Chun Lee Ler,Jeffrey T. Watt +8 more
TL;DR: In this paper, an addressable array test structure is proposed for characterization of transistor variability beyond 3σ away from the mean, based on very compact basic cells which enable a highly efficient layout which has over three times higher normalized device density than similar arrays.
Journal ArticleDOI
Problems With the Continuous Doping TCAD Simulations of Decananometer CMOS Transistors
TL;DR: In this article, the authors compare results from atomistic and continuous simulation of decananometer scale CMOS transistors and demonstrate that there are increasing errors in the doping distributions when device TCAD simulations are calibrated using continuous doping profiles.
Proceedings ArticleDOI
Impact of dynamic variability on SRAM functionality and performance in nano-scaled CMOS technologies
A. Subirats,X. Garros,J. Mazurier,J. El Husseini,O. Rozeau,G. Reimbold,O. Faynot,Gerard Ghibaudo +7 more
TL;DR: In this paper, the authors demonstrate that fast oxide trapping mechanism can be responsible for significant dynamic variability of Vt, gm and Id at circuit operating conditions, and an estimation of the effect of these variabilities has been made using Monte Carlo simulations.
References
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Proceedings ArticleDOI
Analyses of 5σ V th fluctuation in 65nm-MOSFETs using takeuchi plot
Takaaki Tsunomura,Akio Nishida,Fumiko Yano,A.T. Putra,Kiyoshi Takeuchi,S. Inaba,Shiro Kamohara,Kazuo Terada,Toshiro Hiramoto,Tohru Mogami +9 more
TL;DR: Using 1M DMA-TEG, the analyses of 5sigma Vth fluctuation in 65 nm-MOSFETs were carried out in this article, where a B clustering model was proposed to explain this phenomenon.
Proceedings ArticleDOI
Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method
Takaaki Tsunomura,Arun Kumar,Tomoko Mizutani,Chengkuo Lee,Akio Nishida,Kiyoshi Takeuchi,S. Inaba,Shiro Kamohara,Kazuo Terada,Toshiro Hiramoto,Tohru Mogami +10 more
TL;DR: In this article, the causes of drain current local variability are analyzed by decomposing into current variability components, including V TH and G m components, and it is found that effects of current onset variability caused by channel potential fluctuations largely contribute to the current variability.
Proceedings ArticleDOI
SRAM critical yield evaluation based on comprehensive physical / statistical modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations
TL;DR: In this paper, a detailed analysis of transistor intrinsic fluctuations for 65 nm-node and beyond MOSFETs is presented based on comprehensive physical modeling and statistical analysis for more robust design optimizations against variation.