Journal ArticleDOI
SiGe source/drain structure for the suppression of the short-channel effect of sub-0.1-/spl mu/m p-channel MOSFETs
TLDR
In this article, a bandgap engineering technique is proposed for the suppression of the short channel effect and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation.Abstract:
A bandgap engineering technique is proposed for the suppression of the short-channel effect (SCE) and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation. The drain-induced barrier lowering (DIBL) and the charge sharing are suppressed by the presence of the valence band discontinuity between the SiGe source/drain and Si channel. In order to obtain the full advantage of this structure, it is necessary to locate the SiGe layers both at the source/drain regions and the SiSe/Si interface at the pn junction or inside the channel region. The effectiveness increases with the increase of the valence band discontinuity (Ge concentration). As a result of the suppression of the SCE and the reduction of the minimum gate length, the drain current increases, and thus high-speed operation can be realized with this technique.read more
Citations
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Journal ArticleDOI
Considerations for Ultimate CMOS Scaling
TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Journal ArticleDOI
A unified model for insulator selection to form ultra-low resistivity metal-insulator-semiconductor contacts to n-Si, n-Ge, and n-InGaAs
TL;DR: In this article, a unified model for low resistivity metal-insulator-semiconductor (M-I-S) ohmic contact was developed for low conduction band offset.
Journal ArticleDOI
Design of high speed Si/SiGe heterojunction complementary metal–oxide–semiconductor field effect transistors with reduced short-channel effects
Pei-Wen Li,W. M. Liao +1 more
TL;DR: In this article, a planar CMOS structure was proposed in which a strained SiGe layer (the hole channel) and a strained si layer(the electron channel) grown on relaxed SiGe wells are designed for p-and n-MOSFETs, respectively, to provide better current drive capability.
Journal ArticleDOI
Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique
Y. Jiang,Navab Singh,Tsung-Yang Liow,W.Y. Loh,Subramanian Balakumar,Keat Mun Hoe,C.H. Tung,Vladimir Bliznetsov,S.C. Rustagi,Guo-Qiang Lo,D. S. H. Chan,Dim-Lee Kwong +11 more
TL;DR: In this article, a top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si0.7Ge0.3) to channel (Si 0.3Ge 0.7) regions, is presented.
Journal ArticleDOI
Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications
TL;DR: In this article, the authors proposed metaloxide-semiconductor field effect transistor (MOSFET) types featuring additional L-shaped counterdoped areas in the source and/or drain regions of silicon-on-insulator (SOI) MOSFets to reduce drain-induced barrier lowering (DIBL) through the buried oxide (BOX) layer.
References
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Journal ArticleDOI
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Journal ArticleDOI
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Journal ArticleDOI
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