Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes

TLDR: The physical layer of a high-speed serial interface for chip-to-chip communication, targeting low cost and ultra-low power IoT end-nodes, is reported, designed to tolerate significant clock jitter and minimize area and power of supporting circuitry.

Abstract: We report on the design of the physical layer of a high-speed serial interface for chip-to-chip communication, targeting low cost and ultra-low power (mW) IoT end-nodes. Two differential lanes (one pair per direction) are used to transmit/receive NRZ symbols at 1Gpbs with embedded clock. The energy-per-bit is lower than 1pJ/bit, thanks to a careful selection of termination impedance and voltage swing, tuned for moderate speed and short distance (2cm). The transceiver is designed to tolerate significant clock jitter, so that it can work with a half-rate clock shared with the rest of the chip, thereby minimizing area and power of supporting circuitry.