Showing papers on "Adder published in 1995"

Use of minimum-adder multiplier blocks in FIR digital filters

Abstract: The computational complexity of VLSI digital filters using fixed point binary multiplier coefficients is normally dominated by the number of adders used in the implementation of the multipliers. It has been shown that using multiplier blocks to exploit redundancy across the coefficients results in significant reductions in complexity over methods using canonic signed-digit (CSD) representation, which in turn are less complex than standard binary representation. Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time. Significant savings in filter implementation cost over existing techniques result in all three cases. For a given wordlength, it was found that a threshold set size exists above which the multiplier block is extremely likely to be optimal. In this region, design computation time is substantially reduced. >

Architectural power analysis: The dual bit type method

Abstract: This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The dual bit type (DBT) model, however, accounts not only for the random activity of the least significant bits (LSB's), but also for the correlated activity of the most significant bits (MSB's), which contain two's-complement sign information. The resulting model is parameterizable in terms of complexity factors such as word length and can be applied to a wide variety of modules ranging from adders, shifters, and multipliers to register files and memories. Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gate- or circuit-level tools, but while other architecture-level techniques often err by 50-100% or more, the DBT method offers error rates on the order of 10-15%. >

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

Abstract: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

System and method for generating a contrast overlay as a focus assist for an imaging device

Abstract: A system for generating and displaying a contrast false color overlay as a focus assist includes a signal divider, an automatic gain control unit, an adder, a signal reducer and a signal combiner. The signal divider receives a signal representing an image and divides the signal into a red channel signal, a green channel signal and a blue channel signal. The red, green and blue channel signals are input to the signal reducer and respectively reduced by a percentage value. The reduced Green and Blue channel signals are input to the signal combiner and combined with the output of the adder. A luminance signal is also input or generated from the channel signals and is fed to the automatic gain control unit which produces a contrast signal whose brightness is proportional to the contrast in the image. The contrast signal is input to the adder along with a reduced version of the red channel signal where the two signals are added together, and the output of the adder is provided to the combiner. The output of the combiner is then provided to the output device for display of the image. The present invention also comprises a method for adjusting the display to provide a false color contrast overlay as a focus assist, the method comprising the steps of: receiving a signal representing an image; separating the signal into channels; receiving or generating a luminance signal; producing a contrast signal with an amplitude that varies with the contrast in the image from the luminance signal; reducing the contrast signal; reducing the channel signals; combining the reduced contrast signal with one of the reduced channel signals; and generating an image on the output device using the combined signal and the reduced channel signals.

Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

Abstract: In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier. >

Low-power design techniques for high-performance CMOS adders

Abstract: A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 /spl mu/m CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V. >

A new design technique for column compression multipliers

Abstract: In this paper, a new design technique for column-compression (CC) multipliers is presented. Constraints for column compression with full and half adders are analyzed and, under these constraints, considerable flexibility for implementation of the CC multiplier, including the allocation of adders, and choosing the length of the final fast adder, is exploited. Using the example of an 8/spl times/8 bit CC multiplier, we show that architectures obtained from this new design technique are more area efficient, and have shorter interconnections than the classical Dadda CC multiplier. We finally show that our new technique is also suitable for the design of twos complement multipliers. >

Floating point arithmetic unit using modified Newton-Raphson technique for division and square root

Abstract: A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

Diversity reception device

Abstract: A diversity reception device which weights in proportion to the reception level and combines a plurality of reception signals, includes a phase demodulator for demodulating the phase of the reception signal, a converter to output the sine and cosine elements of the reception signal, a sine element adder to add up sine element of each reception signal, and a cosine element adder to add up cosine element of each reception signal. The converter fetches and outputs predetermined values on sine and cosine elements of the reception signal upon input of the reception signal's reception level and phase data that is sent from phase demodulator. Therefore, the present device does not require expensive electronic circuits and can be made of small digital circuits suitable for IC including a memory.

Diagnosing tree-decomposable circuits

Abstract: This paper describes a diagnosis algorithm called structure-based abduction (SAB) which was developed in the framework of constraint networks [12]. The algorithm exploits the structure of the constraint network and is most efficient for near-tree problem domains. By analyzing the structure of the problem domain, the performance of such algorithms can be bounded in advance. We present empirical results comparing SAB with two modelbased algorithms, MBD1 and MBD2, for the task of finding one or all minimal-cardinality diagnoses. MBD1 uses the same computing strategy as algorithm GDE [9]. MBD2 adopts a breadth-first search strategy similar to the algorithm DIAGNOSE [24]. The main conclusion is that for nearly acyclic circuits, such as the N-bit adder, the performance of SAB being linear provides definite advantages as the size of the circuit increases.

114 MFLOPS logarithmic number system arithmetic unit for DSP applications

Abstract: An arithmetic core for DSP applications, comprising two multiplier/dividers and an adder/subtractor, using logarithmic number system (LNS) arithmetic, is described. For most operands, precision better than the worst-case precision of IEEE 754 is obtained. Three operations per cycle are performed using 69k transistors integrated in a 16 mm/sup 2/ core in 1.2 /spl mu/m CMOS, offering better performance than the best previous result in only 43% of the area. The use of a new interleaved memory ROM structure and a second-order function interpolator are the key techniques that result in reduced area. This modest area allows several core units to be integrated on a chip for high performance DSP applications.

Parallel reduced area multipliers

Abstract: As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.

Programmable function unit as parallel multiplier cell

Abstract: A field programmable gate array (FPGA) includes at least one programmable function unit (PFU) which comprises input lines, output lines, and a look-up table (LUT) for generating various functions in response to a configuration bit stream. A first function is an adder/subtracter in which the first input line provides an add/subtract control signal to a multiplexer coupled to a full-adder. The multiplexer determines whether a data bit or its complement is coupled to the full-adder. A second function is an AND gate coupled to the full-adder in which the first input line provides a data bit to the AND gate. The second function provides a basic cell for a parallel multiplier. Furthermore, the first input line may be used as a control line or a data line for a general logic function, depending on the PFU function.

Spread spectrum multipath processor system and method

Abstract: A spread-spectrum system and method for providing high capacity communications through multipath compensation A multipath processor including a first plurality of correlators, a second plurality of correlators, a first adder, a second adder, and a selector device or a combiner device is provided for tracking a spread-spectrum signal arriving in a plurality of groups The first plurality of correlators despreads a first group of spread-spectrum signals as a first group of despread signals which are added by the first adder to generate a first combined-despread signal The second plurality of correlators despreads a second group of spread-spectrum signals as a second group of despread signals which are added by the second adder to generate a second combined-despread signal The selector device selects either the first or the second combined-despread signal and outputs the selected signal Alternatively, the combiner device combines the first and the second combined-despread signals and outputs the combined signal

Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters

Abstract: This paper presents a method to find the minimum number of adders for implementing a multiplier of a given multiplicand and the corresponding structure to realize it. In comparison with the widely used structure based on the canonic signed digit (CSD) expression of multiplicands, the number of adders required by using our structure is not more than that of the CSD structure for any multiplicand. The contiguous range of integer multiplicands whose corresponding multiplications can be implemented by no more than a given number of adders increases exponentially with the increase of the number of adders allowed. It is shown that the ratio of the largest contiguous integer range of our structure to that of the CSD structure is equal to 10.76 and 64.43, respectively, for using no more than 4 and 5 adders. Our method for replacing multipliers with shifters and adders is applied to the design of multiplierless digital filters. Experimental results show that the normalized peak ripples of the filters designed by our method is decreased by up to 4.2 dB over those obtained by the corresponding design method based on the CSD expression of filter coefficients. >

Delay balanced multipliers for low power/low voltage DSP core

Abstract: A simple but effective technique, which synchronizes the propagation of signals at each full adder stage, has cut the power dissipation of an array multiplier down to equal to or less than that of a Wallace-tree multiplier with a minimal penalty in performance and layout area. This delay balanced array multiplier is a strong candidate for low power and small area DSP core for portable equipment.

Field programmable gate array logic module configurable as combinational or sequential circuits

Abstract: A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 1800 Boolean combinational functions on each output 431-432, to operate as a full adder with sum and carry outputs, or to form the sequential function of a D-latch or a D-flipflop. The logic module has ten input terminals 411-418, 421-422 and two output terminals 431-432. The logic module is comprised of two-input multiplexors 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100. The D-latch and D-flipflop have a preset input terminal 415 and a clear input terminal 414. Furthermore, the D-latch can be configured to be latched on either a low level or a high level clock signal on terminal 411, while the D-flipflop can be configured to be triggered by either a low to high transition or a high to low transition of a clock signal on terminal 411. A logic module 401 can be configured to provide both a Q and !Q outputs of the D-latch or D-flipflop on output terminals 431-432. A logic module 402 can be configured to additionally provide a circuit of two D-latches.

Digital video system and methods for efficient rendering of superimposed vector graphics

Abstract: Video system and methods are described for improved image processing (e.g., anti-aliasing) of digital images. The video system includes a shift register component interposed (operably) between video memory and video digital-to-analog components. In this fashion, the shift register stores, at any given time, a collection of pixel values which have been scanned (read) out of the video memory. The shift register is adapted so that a neighborhood of pixel values is available at a given instance for a current pixel from the image stored in the video memory. Selected cells of the shift register are adapted to include "taps" which form connections between those cells and the input to a multiplier/adder circuit. Once a given neighborhood of pixel values is supplied to the multiplier/adder circuit, the system may compute a new (i.e., enhanced) pixel value by applying a filter template--a collection of filter weightings or coefficients. This is done for each pixel in the image (or image pair) in parallel with the scan out of video memory.

Error-correcting encoder, error-correcting decoder and data transmitting system with error-correcting codes

Abstract: The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift-register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs. The syndrome generator of the error-correcting decoder of the invention includes a plurality of Galois field multipliers which multiply the coefficients for calculating syndromes for inputting different code symbols in parallel from a plurality of input terminals. The syndrome generator also includes a Galois field adder and a shift-register(s) to obtain the predetermined syndrome generating polynomial. The syndrome generator can obtain the desired syndromes with shifts, the number of which is reduced according to the number of parallel inputs.

Power control circuit for use with transmitter

Abstract: A power control circuit having a saturation preventing control loop including a variable gain amplifier, an RF power amplifier, a directional coupler, a detecting circuit, a comparator, a switch, and an adder. When the signal level of an output signal of the comparator is low, the switch is turned on. When the signal level of the output signal of the comparator is high, the switch is turned off. A system power control loop includes a system power control terminal, the adder, and the variable gain amplifier. Since the saturation preventing control loop is provided with the switch, the saturation preventing control loop operates only when the signal level of the amplified signal is larger than a reference value. The system power control loop can properly operate according to a system power control signal supplied from the system power control terminal.

An MOS current mode logic (MCML) circuit for low-power GHz processors

Abstract: This paper describes a new 0.5 μm MOS Current Mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. Simulated performance comparison with CMOS and bipolar circuits, and experimented results of fabricated MCML circuits are discussed. At 1.2V, the MCML circuit has 90% of the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL (Emitter Coupled Logic) circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5 μm 500 MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500 MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3 V CMOS full adder. GHz frequencies operation of fabricated MCML registers has been examined. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing GHz processors.

General algorithms for a simplified addition of 2's complement numbers

Abstract: Two algorithms for both a simplified carry save and carry ripple addition of 2's complement numbers are presented. The algorithms form the partial products so that they exclusively have positive coefficients which eliminates the need for the common sign bit extension. This results in a reduction of circuit area by up to six full adders per row of adders when partial products are added in an N/2 or Wallace tree. Furthermore, the capacitive load of the intermediate sum and carry sign bit signals decreases by up to a factor of seven which leads to an appropriate reduction of delay. Although the algorithms are derived for multipliers they can always be applied to appropriate adder circuits. >

General algorithms for reduced-adder integer multiplier design

Abstract: The problem of reducing the number of adders required to perform shift-and-add multiplication is addressed for hardware and software applications. Algorithms invented for each of these applications are compared and found to have similar performances in general. Improved results are achieved by selecting the best design of the two.

Mechanical signal processor based on micromechanical oscillators and intelligent acoustic detectors and systems based thereon

Abstract: The present invention concerns mechanical signal processing means comprising a mechanical adder as basic building block. Such a mechanical adder (40), which is a basic element of the present invention, comprises: a first micromechanical member (40.1) being sensitive to a first frequency (f1); and a second micromechanical member (40.2) being sensitive to a second frequency (f2). The two micromechanical members (40.1, 40.2) are coupled via linear coupling means (41) to provide a superposition (sum) of the two frequencies f1 and f2. Based on the above adder, AND-gates and OR gates can be realized by adding further micromechanical members and appropriate linear and non-linear coupling elements.

Optimized binary adder and comparator having an implicit constant for an input

Abstract: A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two different bit cells depending upon whether that bit position in the constant input is a one or a zero. The three-input comparator can be modified to be a three-input adder by using a full carry-propagate adder (CPA). By taking into account a priori restrictions on the possible input operands, these arithmetic circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.

Accumulative parallel counters

Abstract: An accumulative parallel counter represents a true generalization of a sequential counter in that it incorporates the memory feature of an ordinary counter; i.e., it adds the sum of its n binary inputs to a stored value. We examine the design of accumulative parallel counters and show that direct synthesis of such a counter, as opposed to building it from a combinational parallel counter and a fast adder, leads to significant reduction in complexity and delay. While the mere fact that savings can be achieved comes as no surprise to seasoned arithmetic designers, its extent and consequences in designing large-scale (systolic) associative processors, modular multi-operand adders, serial-parallel multipliers, and digital neural networks merits detailed examination. Both simple accumulative parallel counters and their modular versions, that keep the accumulated count module an arbitrary constant p, are dealt with.

CMOS analogue adder

Abstract: A CMOS analogue circuit is proposed that computes the sum of two voltages. The circuit is self-biased, only requires a small number of transistors, and offers good accuracy over a wide range of input values. The design makes no special demands on device aspect ratios and could offer an economic alternative to conventional approaches. Simulation results have shown that total harmonic distortion (THD) is lower than –40 dB for output voltages up to 4 V peak to peak.

ATM cell switch

Abstract: An ATM cell switch includes a plurality of link controllers, each of which has a leaky bucket processor to monitor and control cell flow rates. Each of the leaky bucket processors includes a pair of buckets. Each processor times the arrival of each ATM cell in the respective link controller, calculates the time interval between the reception of two consecutive cells on the same connection, simultaneously determines the resultant level in both of the buckets from the calculated time interval and a stored predetermined regular bucket increment, compares the resultant level with a predetermined maximum level, and discards or changes the CLP of the current cell if the resultant level exceeds the predetermined maximum. According to a preferred embodiment of the invention, timing is effected with a 32-bit timer, but only the least significant 16-bits are used to time stamp cells. The time interval between two cells is calculated with two 16-bit adder/subtractors and two 16-bit buckets are thereby simultaneously controlled. The 32-bit routing table data is split into 16 lsb and 16 msb which are directed to respective of the adder/subtractors. A sequence of simultaneous operations in each of the adder/subtractors determine the eligibility of cells and the resultant bucket levels.

Low-power multiplier design using delayed evaluation

Abstract: A circuit design technique for very low power parallel multipliers is presented. The design uses dynamic CMOS circuits together with a self-timed evaluate signal in such a way that each carry-save or carry-propagate adder within the array evaluates only after all of its inputs have stablized. This technique avoids the spurious switching of internal nodes so that the average power dissipation is minimized. Circuit simulation results are presented which illustrate the power dissipation characteristics of the multiplier.