Showing papers on "Adder published in 2007"
TL;DR: Three kinds of adder designs in quantum-dot cellular automata are proposed, designed and simulated with several different operand sizes and compared according to complexity, area, and delay.
Abstract: Quantum-dot cellular automata (QCA) is an emerging nanotechnology for electronic circuits. Its advantages such as faster speed, smaller size, and lower power consumption are very attractive. The fundamental device, a quantum-dot cell, can be used to make gates, wires, and memories. As such it is the basic building block of nanotechnology circuits. While the physical nature of the nanoscale materials is complicated, the circuit designer can concentrate on the logical and structural design, so the design effort is reduced. Because of its novelty, the current literature shows only simple circuit structures. So this paper broadens the QCA circuit designs with larger circuits and shows analyses based on those designs. This paper proposes three kinds of adder designs in QCA. Ripple carry adders, carry lookahead adders, and conditional sum adders are designed and simulated with several different operand sizes. The designs are compared according to complexity, area, and delay
295 citations
TL;DR: The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized, and has the lowest working Vdd and highest working frequency among all designs using ten transistors.
Abstract: In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered xor/xnor designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-mum process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases
213 citations
TL;DR: This paper analyzes the reasons of the failures of adder designs using QCA technology, and proposes adders that exploit proper clocking schemes.
Abstract: Quantum-dot cellular automata (QCA) is attracting a lot of attention due to its extremely small feature size and ultralow power consumption. Up to now, several adder designs using QCA technology have been proposed. However, it was found that not all of the designs function properly. This paper analyzes the reasons of the failures and proposes adders that exploit proper clocking schemes
211 citations
01 Jan 2007
TL;DR: A Genetic Algorithm is presented which is capable of evolving 100% functional arithmetic circuits, based on evolving the functionality and connectivity of a rectangular array of logic cells and is modelled on the resources available on the Xilinx 6216 FPGA device.
Abstract: A Genetic Algorithm is presented which is capable of evolving 100% functional arithmetic circuits. Evolved designs are presented for one-bit, two-bit adders with carry, and two and three-bit multipliers and details of the 100% correct evolution of three and four-bit adders. The largest of these circuits are the most complex digital circuits to have been designed by purely evolutionary means. The algorithm is able to re-discover conventionally optimum designs for the one-bit and two-bit adders, but more significantly is able to improve on the conventional designs for the two-bit multiplier. By analysing the history of an evolving design up to complete functionality it is possible to gain insight into evolutionary process. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells and is modelled on the resources available on the Xilinx 6216 FPGA device. Further work is described about plans to evolve the designs directly onto this device.
132 citations
27 May 2007
TL;DR: An adder graph type algorithm for solving the MCM problem is introduced with a novel heuristic inspired by difference methods and it is shown that the results is as good or better as previous state of the art under most conditions.
Abstract: Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. An adder graph type algorithm for solving the MCM problem is introduced with a novel heuristic inspired by difference methods. It is shown that the results is as good or better as previous state of the art under most conditions. Furthermore, the proposed algorithm does not rely on look-up tables.
111 citations
TL;DR: This work proposes and simulates all-optical simultaneous half-adder, half-subtracter, and OR logic gate at 40 Gbit/s based on the cascaded sum-and difference-frequency generation (SFG+DFG) using only one periodically poled lithium niobate (PPLN) waveguide.
Abstract: We propose and simulate all-optical simultaneous half-adder, half-subtracter, and OR logic gate at 40 Gbit/s based on the cascaded sum-and difference-frequency generation (SFG+DFG) using only one periodically poled lithium niobate (PPLN) waveguide. The SFG and DFG processes generate the Borrow and Carry outputs, respectively. The Sum/Difference and OR are obtained by properly combining the outputs from PPLN after SFG+DFG. The eye diagrams, pulse width, quality-factor (Q-factor), extinction ratio (ER), and tunability are calculated and discussed,showing impressive operation performance.
106 citations
TL;DR: A hardware-oriented fast algorithm based on the systolic array and 2-D adder tree architecture, a ladder-shaped search window data arrangement and an advanced searching flow are proposed to efficiently support inter-candidate DR and reduce latency cycles.
Abstract: In an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR). In this paper, a hardware-oriented fast algorithm is proposed with the intra-/inter-candidate DR considerations. In addition, based on the systolic array and 2-D adder tree architecture, a ladder-shaped search window data arrangement and an advanced searching flow are proposed to efficiently support inter-candidate DR and reduce latency cycles. According to the implementation results, 97% computational complexity is saved by the proposed fast algorithm. In addition, 77.6% memory bandwidth is further saved with the proposed DR techniques at architecture level. In the ultra-low-power mode, the power consumption is 2.13 mW for real-time encoding CIF 30-fps videos at 13.5-MHz operating frequency
105 citations
TL;DR: This study presents a novel design for QCA cells and another possible and unconventional scheme for majority gates and proves that how this reduction method decreases gate counts and levels in comparison to the other previous methods.
Abstract: Quantum-dot Cellular Automata (QCA) is a novel and potentially attractive technology for implementing computing architectures at the nano-scale. The basic Boolean primitive in QCA is the majority gate. In this study we present a novel design for QCA cells and another possible and unconventional scheme for majority gates. By applying these items, the hardware requirements for a QCA design can be reduced and circuits can be simpler in level and gate counts. As an example, a one bit QCA adder is constructed by applying our new scheme. Beside, we prove that how our reduction method decreases gate counts and levels in comparison to the other previous methods.
101 citations
11 Apr 2007
TL;DR: A low-power high-speed CMOS full adder core is proposed for embedded system based on a new three-input exclusive OR (3-XOR) design that is composed of pass-transistor logic and static CMOS logic.
Abstract: In this paper, a low-power high-speed CMOS full adder core is proposed for embedded system. Based on a new three-input exclusive OR (3-XOR) design, the new hybrid full adder is composed of pass-transistor logic and static CMOS logic. The main design objectives for the full adder core are providing not only low power and high speed but also with driving capability. Using TSMC CMOS 0.35-mum technology, the characteristics of the experimental circuit compared with prior literature show that the new adder improves 1.8% to 35.6% in power consumption, 11.7% to 41.2% in time delay of Co, and 13.7% to 91.4% in power-delay product of Co. The circuit is proven to have the minimum power consumption and the fastest response of carry out signal among the adders selected for comparison. Due to the low-power and high-speed properties, both the new exclusive OR circuit and the new full adder can be efficiently integrated in a system-on-a-chip (SoC) or an embedded system.
95 citations
94 citations
IBM1
TL;DR: A compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented, demonstrating a >10X density increase over traditional VLSI fuse circuits.
Abstract: Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65 nm SOI CMOS. A 20 mus programming time at 1.5 V is achieved by asymmetrical scaling of the fuse and a shared differential sensing scheme. Having zero process cost adder, eFUSE is fully compatible with standard VLSI manufacturing.
TL;DR: This paper proposes quantum realization of a ternary full-adder using macro-level Ternary Feynman and Toffoli gates built on the top of ion-trap realizable ternaries 1-qutrit and Muthukrishnan-Stroud gates and proposes realization ofA ternARY parallel adder with partially-look-ahead carry.
TL;DR: This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers, and a range of adders from 4 to 128 bits is designed using a 0.5-mum CMOS technology.
Abstract: Carry-select adders are one of the faster types of adders. This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers. The multiplexers used in the adder are also totally self-checking. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed. Adders of arbitrary size can be constructed by cascading the appropriate number of such 2-bit adders. A range of adders from 4 to 128 bits is designed using this approach employing a 0.5-mum CMOS technology. The transistor overhead in implementing these self-checking adders varies from 19.51% to 20.94%, and the area overhead varies from 16.07% to 20.67% compared to adders without built-in self-checking capability.
TL;DR: In this article, it was shown that polydimethylsiloxane membrane valve structures can be configured to function as transistors in pneumatic digital logic circuits (AND, OR, NOT, NAND, and XOR).
Abstract: It is shown that microfabricated polydimethylsiloxane membrane valve structures can be configured to function as transistors in pneumatic digital logic circuits. Using the analogy with metal-oxide-semiconductor field-effect transistor circuits, networks of pneumatically actuated microvalves are designed to produce pneumatic digital logic gates (AND, OR, NOT, NAND, and XOR). These logic gates are combined to form 4- and 8-bit ripple-carry adders as a demonstration of their universal pneumatic computing capabilities. Signal propagation through these pneumatic circuits is characterized, and an amplifier circuit is demonstrated for improved signal transduction. Propagation of pneumatic carry information through the 8-bit adder is complete within 1.1 s, demonstrating the feasibility of integrated temporal control of pneumatic actuation systems. Integrated pneumatic logical systems reduce the number of off-chip controllers required for lab-on-a-chip and microelectromechanical system devices, allowing greater complexity and portability. This technology also enables the development of digital pneumatic computing and logic systems that are immune to electromagnetic interference.
TL;DR: The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption and a very high speed and this enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications.
01 Aug 2007
TL;DR: This paper investigates the performance of parallel prefixAdders implemented with FPGA technology and reports on the area requirements and critical path delay for a variety of classical parallel prefix adder structures.
Abstract: Parallel Prefix Adders have been established as the most efficient circuits for binary addition. Their regular structure and fast performance makes them particularly attractive for VLSI implementation. The classical parallel prefix adder structures that have been proposed over the years optimize for logic depth, area, fan-out and interconnect count of the logic circuits. This paper investigates the performance of parallel prefix adders implemented with FPGA technology. We report on the area requirements and critical path delay for a variety of classical parallel prefix adder structures.
TL;DR: Qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions.
Abstract: A new modulo 2 n +1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions
01 Sep 2007
TL;DR: Four different types of 10 transistor (10-T) based full adder are proposed using a new design methodology called GDI (gate-diffusion input) to test the performance of the proposed adders.
Abstract: A full adder is one of the most commonly used digit circuit components, many improvements have been made to refine the architecture of a full adder. In this paper, 4 different types of 10 transistor (10-T) based full adder are proposed using a new design methodology called GDI (gate-diffusion input). In the meantime, a complete verification and comparison is also carried out to test the performance of the proposed adders. According to our test results, one of the proposed 10-T full adders is better than the prior designs which makes it a better alternative.
23 Apr 2007
TL;DR: It is shown that the fractional-step method employing central difference schemes can be expressed as a systolic algorithm, and therefore the systolics architecture is suitable for a dedicated processor to the flow solver.
Abstract: This paper presents an FPGA-based flow solver based on the systolic architecture. We show that the fractional-step method employing central difference schemes can be expressed as a systolic algorithm, and therefore the systolic architecture is suitable for a dedicated processor to the flow solver. We have designed a 2D systolic array of cells, each of which has a micro-programmable data-path containing a MAC (multiplication and accumulation) unit and a local memory to store necessary data for computational fluid dynamics. With ALTERA Stratix II FPGA, we implemented 96(= 12 times 8) cells running at 60 MHz. Since the MAC unit has both an adder and a multiplier for single-precision floating-point numbers, the total peak performance is 11.5(= 96times60 MHztimes2) GFlops. We made a choice of 2D square driven cavity flow as a benchmark computation based on the fractional-step method. For this computation, the FPGA-based processor running only at 60 MHz achieved 7.14 and 6.41 times faster computations than Pentium4 processor at 3.2 GHz and Itanium2 at 1.4 GHz, respectively.
TL;DR: This work identifies reliability thresholds in the ability of defective crossbars to implement boolean logic, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components.
Abstract: Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect-free crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify reliability thresholds in the ability of defective crossbars to implement boolean logic. These thresholds vary among different implementations of the same logical formula, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components. We illustrate these choices for binary adders. For instance, one adder implementation yields functioning circuits 90% of the time with 30% defective crossbar junctions using an area only 1.8 times larger than the minimum required for a defect-free crossbar. We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.
25 Jun 2007
TL;DR: While a design with fully custom sizes can be extremely tedious to layout, it is shown that custom sizing can be used as a guide to group different gates in the design, resulting in a manageable layout overhead without significant loss of energy efficiency.
Abstract: In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32- bit adder topologies, to determine how architectural features and design techniques affect energy efficiency. Optimizing different adders for the supply and threshold voltages, and transistor sizing, we show that topologies with the least number of logic stages having an average fanin of two per stage, and fewest wires are most energy efficient. While a design with fully custom sizes can be extremely tedious to layout, we show that custom sizing can be used as a guide to group different gates in the design, resulting in a manageable layout overhead without significant loss of energy efficiency.
TL;DR: This work considers the problem of multioperand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal numbers, and treats the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells.
Abstract: Decimal arithmetic has been revived in recent years due to the large amount of data in commercial applications. We consider the problem of multioperand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. We adopt the latter approach, which is particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion moreover allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the BD conversion as a design tool.
27 May 2007
TL;DR: The critical delays and hardware complexities of conventional MAC architectures are examined to derive at a unit with low critical delay and low hardware complexity to realize the area-efficient and high speed MAC unit proposed in this work.
Abstract: A high speed and area-efficient merged multiply accumulate (MAC) units is proposed in this work. To realize the area-efficient and high speed MAC unit proposed in this work, first we examine the critical delays and hardware complexities of conventional MAC architectures to derive at a unit with low critical delay and low hardware complexity. The new architecture is based on binary trees constructed using a modified 4:2 compressor circuits. Reducing the overall area is achieved by the full utilization of the compressors instead of putting zeros in free inputs. Increasing the speed of operation is achieved by avoid using the modified compressor in the critical path. Feeding the bits of the accumulated operand into the summation tree before the final adder helps to increase the speed too. The proposed MAC unit and the previous merged MAC unit are mapped on a field programmable gate array (FPGA) chip, in order to compare between them. The simulation result shows that the proposed system for 8-bit, 16-bit, and 32-bit MAC unit reduces area by 6.25%, 3.2 %, and 2.5% and increases the speed by 14%, 16%, and 19% respectively. The experimental test for the proposed 8-bit MAC is done using XESS demo board (XSA-100, Spartan-X2S100tq144).
09 Jul 2007
TL;DR: This paper designs a serial adder and a ripple carry adder, which occupy a fraction of area compared to a previous noise rejecting design, have the smallest carry path delay, and are pipelined on ultra-fine-grained cellular level.
Abstract: This paper demonstrates designing adders on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement logic and all interconnections with only one homogeneous layer of cells. This promising technology has a structural noise path problem, causing general circuit failure. We propose a robust full adder, which avoids the fore mentioned noise paths by careful clocking organization. We construct a serial adder and a ripple carry adder, which occupy a fraction of area compared to a previous noise rejecting design, have the smallest carry path delay, and are pipelined on ultra-fine-grained cellular level. The modular layouts are verified with the freely available QCADesigner simulator, using the coherence vector model.
27 May 2007
TL;DR: A new 4 times 4 reversible gate termed `OTG' (online testable gate) is proposed suitable for online testability in reversible logic circuits and is shown better than the recently proposed R1 gate, in terms of computation complexity.
Abstract: Reversible logic is emerging as a promising computing paradigm having its applications in low power VLSI design, quantum computing, nanotechnology and optical computing. In this paper, a new 4 times 4 reversible gate termed `OTG' (online testable gate) is proposed suitable for online testability in reversible logic circuits. OTG can also work singly as a reversible full adder with a bare minimum of two garbage outputs. OTG is shown better than the recently proposed R1 gate (introduced for providing online testability in reversible logic circuits), in terms of computation complexity. The proposed reversible gate is combined with the existing 4 times 4 Feynman gate to design online testable reversible adders such as ripple carry adder, carry skip adder and BCD adder. The efficient reversible design of two pair rail checker is also shown in this paper. The testable reversible circuits proposed in this work are shown to be better than the recently proposed testable designs in terms of number of reversible gates, garbage outputs and unit delay
01 Oct 2007
TL;DR: A compressed distributed arithmetic architecture for 2D 8times8 DCT is presented, which offers high speed and small area and has a great improvement on computing speed and reducing area.
Abstract: Discrete cosine transform (DCT) plays an important role in image and video compression, but computing a two-dimensional (2D) DCT, a large number of multiplications and additions are required in a direct approach. Multiplications, which are the most time-consuming and expensive operations in simple processor, can be completely avoided in our proposed architecture for multiple channel real-time image compression. In this paper, a compressed distributed arithmetic architecture for 2D 8times8 DCT is presented, which offers high speed and small area. The basic architecture consists of a ID row DCT followed by a transpose register array and another ID column DCT, in which an 8-input ID DCT structure only requires 15 adders to build a compressed adder matrix and no ROM is needed. Compared with other architectures available, it has a great improvement on computing speed and reducing area.
TL;DR: A novel memory-access and computation efficient full-search block-matching hardware architecture that can achieve the minimum off-chip memory bandwidth and the maximum computational performance for H.264/AVC integer motion estimation is presented.
Abstract: Motion estimation (ME) is the most critical component of a video coding system, and it also dominates the major part of computation complexity and memory bandwidth. For H.264/AVC integer motion estimation (IME), this paper presents a novel memory-access and computation efficient full-search block-matching hardware architecture. With the highest level of on-chip data reuse, one-access for off-chip reference pixels is achieved, and the off-chip memory bandwidth is thus minimized. By distributed data caching and virtual connection of reference picture boundaries, the data traffic scheduling is simple, regular and efficient. The computation engine employs a two-dimensional (2-D) systolic processor array to calculate the absolute differences in single-instruction multiple-data (SIMD) manner, and 2-D adder trees to sum up the absolute differences, all with 100% utilization. The proposed architecture fully supports variable block-size matching of H.264/AVC, and can produce 41 sums of absolute differences (SADs) for one search point every cycle without bubble. The architecture is described in parameterized design, and an implementation for standard-definition digital TV encoding applications is presented. Theoretical analysis and experimental results show that, the proposed architecture can achieve the minimum off-chip memory bandwidth and the maximum computational performance.
27 Aug 2007
TL;DR: This paper incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks and found that power savings, energy per computation savings, and yield enhancement were higher than the conventional adders and multipliers implemented in the 70nm BPTM technology.
Abstract: In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage Simulation results show power savings of upto 29%, energy per computation savings of upto 255% and yield enhancement of upto 111% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9] Maximum area and throughput penalty obtained were 10% and 3% respectively
26 Sep 2007
TL;DR: Examination of reliability considerations of several sample circuits when implemented in a molecular QCA technology shows that component error rates must be at or below 10~4 for an adder to function with 99% reliability and that the straight wire and majority gate are the most critical components to each circuit's reliability.
Abstract: Since nanoelectronic devices are likely to be defective and error-prone, developing an understanding of circuit reliabilities and critical components will be required To this end, this paper examines reliability considerations of several sample circuits when implemented in a molecular QCA technology Probabilistic transfer matrices are used to analyze an XOR, crossover, adder, and an adder using triple modular redundancy This provides insight in answering how reliable emerging circuit components must be to have a reliable circuit and which of these components are the most critical As will be shown, component error rates must be at or below 10~4 for an adder to function with 99% reliability and that the straight wire and majority gate are the most critical components to each circuit's reliability It is also shown that the common assumption made in triple modular redundancy theory that only gates fail is insufficient for QCA
TL;DR: A comprehensive SOA model is put forward to investigate the output characteristics of the all-optical adders, and numerical simulation results demonstrate the influence of these key parameters, including input pulse peak power, pulsewidth, repetition rate, and OBF characteristics.