scispace - formally typeset
Search or ask a question

Showing papers on "Capacitance published in 1999"


Journal ArticleDOI
TL;DR: Chronopotentiometry is found to be a convenient and fast experimental method to critically evaluate the potential stability of different types of ion-selective electrodes.
Abstract: Demanding analytical applications such as on-line process analysis and clinical analysis require robust, reliable, and maintenance-free ion sensors of high potential stability. In this work the stability of the electrode potential of all-solid-state ion-selective electrodes using conducting polymers as ion-to-electron transducers is critically evaluated by using chronopotentiometry and electrochemical impedance spectroscopy. This study is focused on the relationship between the potential stability of the electrode and the capacitance of the solid contact where ion-to-electron transduction takes place. The influence of this capacitance on the potential stability of all-solid-state ion-selective electrodes is studied experimentally by using conducting polymer layers of different thickness as solid contacts in potassium ion-selective electrodes based on a solvent polymeric membrane. Because of its excellent environmental stability, the conducting polymer poly(3,4-ethylenedioxythiophene) (PEDOT) is used as a model compound for the solid contact material. Chronopotentiometry is found to be a convenient and fast experimental method to critically evaluate the potential stability of different types of ion-selective electrodes.

550 citations


Journal ArticleDOI
TL;DR: In this article, a new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies for a 1.7 nm SiO/sub 2/ capacitor.
Abstract: As oxide thickness is reduced below 2.5 nm in MOS devices, both series and shunt parasitic resistances become significant in capacitance-voltage (C-V) measurements. A new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies. This technique is demonstrated for a 1.7 nm SiO/sub 2/ capacitor.

492 citations


Patent
07 Sep 1999
TL;DR: Pulse circuits as mentioned in this paper are made from sets of three or more electrical switching elements arranged so that each of the switching elements has one side electrically connected to either a supply voltage or to an electrical ground.
Abstract: Pulse circuits for measuring the capacitance to ground of a plate may be used in control equipment to provide an indication of the proximity of a person or object to be sensed. Pulse circuits are disclosed that are made from sets of three or more electrical switching elements arranged so that each of the switching elements has one side electrically connected to either a supply voltage or to an electrical ground. These arrangements are compatible with existing integrated circuit fabrication technology. In addition, the circuitry can be configured as a proximity sensing switch that requires only a two wire connection to a host apparatus.

399 citations


Patent
20 Oct 1999
TL;DR: The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.
Abstract: Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower-trench based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.

375 citations


Journal ArticleDOI
TL;DR: In this paper, the authors measured the curvature change upon the removal of a thin film, and found the magnitude of the residual stress to be 610 MPa in a separate experiment, and simultaneously recorded the capacitance change of the film.
Abstract: Barium strontium titanate thin films are being developed as capacitors in dynamic random access memories These films, grown on silicon substrates, are under tensile residual stress By a converse electrostrictive effect, the in-plane tensile stress reduces the capacitance in the thickness direction of the film We measured the substrate curvature change upon the removal of the film, and found the magnitude of the residual stress to be 610 MPa In a separate experiment, we applied a force to vary the stress in a film on a substrate, and simultaneously recorded the capacitance change of the film The measurements quantify the effect of stress on thin film capacitance The stress free capacitance was found to be 23% higher than the capacitance under residual stress

292 citations


Patent
11 Mar 1999
TL;DR: In this paper, a solid-state image pickup apparatus including a photoelectric conversion unit (PD), transfer switch (MTX), capacitance for holding the transferred signal charges, and amplification transistor (MSF) for outputting a signal corresponding to the signal charges held by the capacitance.
Abstract: This invention is to provide a solid-state image pickup apparatus including a photoelectric conversion unit (PD), transfer switch (MTX) for transferring signal charges from the photoelectric conversion unit, capacitance for holding the transferred signal charges, and amplification transistor (MSF) for outputting a signal corresponding to the signal charges held by the capacitance. The amplification transistor includes a capacitance unit (CFD) having the first capacitance value and an additive capacitance unit (Cox) for adding a capacitance to the capacitance unit to increase the first capacitance value and obtain the second capacitance value. A signal read-out from the amplification transistor has a first read-out mode in which a signal is read out while keeping the signal charges held by the capacitance unit and additive capacitance unit, and a second read-out mode in which a signal is read out while keeping the signal charges held by the capacitance unit.

275 citations


Journal ArticleDOI
01 Jan 1999
TL;DR: In this article, the authors presented a highly sensitive AC-based capacitance measuring circuit, which has been specially designed for this purpose, and a PC-based ECT system with this circuit.
Abstract: Electrical capacitance tomography (ECT) is a new technology that is used to visualise the internal behaviour of industrial processes comprising dielectric components. A particular difficulty with capacitance measurement for tomography is that the stray capacitance to earth of an ECT sensor is large (/spl sim/150 pF) compared with the interelectrode capacitance to be measured (usually <0.5 pF), and the measurement range is wide (0.01-2 pF). The authors present a highly sensitive AC-based capacitance measuring circuit, which has been specially designed for this purpose, and a PC-based ECT system with this circuit. Experimental results show that this ECT system can measure as small as 0.01 pF capacitance with 0.0002 pF error, and could collect tomographic image data at more than 100 frames per second.

270 citations


Proceedings ArticleDOI
L. Lorenz1, G. Deboy1, A. Knapp1, Martin Marz1
26 May 1999
TL;DR: The CoolMOS/sup TM/ as discussed by the authors, a new high voltage power MOSFET based on the concept of charge compensation, has been introduced, which shows both a very small input capacitance and a strongly nonlinear output capacitance.
Abstract: Recently, a new technology for high voltage power MOSFETs has been introduced: the CoolMOS/sup TM/. Based on the new device concept of charge compensation, the R/sub DS(on)/ area product for e.g. 600 V transistors has been reduced by a factor of 5. The devices show no bipolar current contribution like the well known tail current observed during the turn-off phase of IGBTs. CoolMOS/sup TM/ virtually combines the low switching losses of a MOSFET with the on-state losses of an IGBT. Furthermore, the dependence of R/sub DS(on)/ on the breakdown voltage has been redefined. The more than square-law dependence in the case of standard MOSFET has been broken and a linear voltage dependence achieved. This opens the way to new fields of application even without avalanche operation. System miniaturization, higher switching frequencies, lower circuit parasitics, higher efficiency, and reduced system costs are pointing the way towards future developments. Not only has the new technology achieved breakthrough at reduced R/sub DS(on)/ values, but new benchmarks have also been set for the device capacitances. Due to chip shrinkage and a novel internal structure, the technology shows both a very small input capacitance and a strongly nonlinear output capacitance. The drastically lower gate charge facilitates and reduces the cost of controllability, and the smaller feedback capacitance reduces the dynamic losses. With this new technology, the minimum R/sub DS(on)/ values in all packages are being redefined in the important 600-1000 V categories.

251 citations


Journal ArticleDOI
TL;DR: In this article, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability.
Abstract: Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage.

228 citations


Journal ArticleDOI
10 Sep 1999-Science
TL;DR: In this article, a capacitance standard based directly on the definition of capacitance was built, and single-electron tunneling devices were used to place N electrons of charge e onto a cryogenic capacitor C, and the resulting voltage change ΔV was measured.
Abstract: A capacitance standard based directly on the definition of capacitance was built. Single-electron tunneling devices were used to place N electrons of charge e onto a cryogenic capacitor C, and the resulting voltage change ΔV was measured. Repeated measurements ofC = Ne/ΔV with this method have a relative standard deviation of 0.3 × 10–6. This standard offers a natural basis for capacitance analogous to the Josephson effect for voltage and the quantum Hall effect for resistance.

224 citations


Journal ArticleDOI
TL;DR: In this article, the ideal trend of coating capacitance is compared with some real experimental results, discussing the reasons of disagreement and the limits of the model which seem to be in many cases insufficient and too simple to explain the actual water uptake processes.

Patent
19 Jul 1999
TL;DR: In this paper, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shape semiconductor regions, is used as a switching element.
Abstract: In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.

Journal ArticleDOI
TL;DR: Mechanisms influencing specific capacitance and charge loss of BSTO films are described, as are the requirements for the electrode and barrier materials used in stacked-capacitor structures, with emphasis given to the properties of the Pt/TaSi(N) electrode/barrier system.
Abstract: Thin films of barium-strontium titanate (Ba,Sr)TiO3 (BSTO) have been investigated for use as a capacitor dielectric for future generations of dynamic random-access memory (DRAM). This paper describes progress made in the preparation of BSTO films by liquid-source metal-organic chemical vapor deposition (LS-MOCVD) and the issues related to integrating films of BSTO into a DRAM capacitor. Films of BSTO deposited on planar Pt electrodes meet the electrical requirements needed for future DRAM. The specific capacitance and charge loss are found to be strongly dependent on the details of the BSTO deposition, the choice of the lower electrode structure, the microstructure of the BSTO, the post-electrode thermal treatments, BSTO dopants, and thin-film stress. Films of BSTO deposited on patterned Pt electrodes with a feature size of 0.2 µm are found to have degraded properties compared to films on large planar structures, but functional bits have been achieved on a DRAM test site at 0.20-µm ground rules. Mechanisms influencing specific capacitance and charge loss of BSTO films are described, as are the requirements for the electrode and barrier materials used in stacked-capacitor structures, with emphasis given to the properties of the Pt/TaSi(N) electrode/barrier system. Major problems requiring additional investigation are outlined.

Patent
21 Jun 1999
TL;DR: In this paper, a sensor matrix array has a characteristic capacitance on horizontal and vertical conductors connected to sensor pads, and the capacitance changes as a function of the proximity of an object or objects to the sensor matrix.
Abstract: A proximity sensor system includes a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by digital circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed.

Journal ArticleDOI
TL;DR: The scanning capacitance microscope (SCM) provides a direct method for mapping the dopant distribution in a semiconductor device on a 10 nm scale as mentioned in this paper, which is critical for the development, optimization, and understanding of future ULSI processes and devices.
Abstract: ▪ Abstract The scanning capacitance microscope (SCM) provides a direct method for mapping the dopant distribution in a semiconductor device on a 10 nm scale. This capability is critical for the development, optimization, and understanding of future ULSI processes and devices. The basic elements of the SCM and its application to nanometer scale metal oxide semiconductor (MOS) capacitor measurements are described. Experimental SCM methods are reviewed. Basic measurements show that nanometer scale capacitance-voltage relations are understood. High-quality probe tips and surfaces are critical for obtaining accurate measurements of two-dimensional dopant profiles. Quantitative modeling of SCM measurement is described for converting raw SCM data to dopant density. An inverse modeling method is presented. Direct comparison between secondary ion mass spectroscopy (SIMS) and SCM-measured dopant profiles are made. Quantitative junction measurements and models are discussed and images of small transistors are presented.

Journal ArticleDOI
TL;DR: In this article, a 7.2V, 1.25 Ah sealed lithium-ion rechargeable battery has been studied for estimating its state-of-charge (SOC) by AC impedance.
Abstract: A 7.2V, 1.25 Ah sealed lithium-ion rechargeable battery has been studied for estimating its state-of-charge (SOC) by AC impedance. The dispersion of impedance data over the frequency range between 100 kHz and 25 mHz comprises an inductive part and two capacitive parts. As the inductive behaviour of the battery is attributed to the porous nature of the electrodes, only the capacitive components have been examined. The data obtained at several SOC values of the battery have been analyzed by a non-linear least-squares fitting procedure. The presence of two depressed semicircles in the capacitive region of the Nyquist plots necessitated the use of an electrical equivalent circuit containing constant phase elements instead of capacitances. The impedance parameters corresponding to the low-frequency semicircle have been found useful for predicting the SOC of the battery, mainly because the magnitude of these parameters and their variations are more significant than those of the high-frequency semicircle. The frequency maximum (f(max)) of the semicircle, the resistive component (Z') corresponding to f(max), the phase angle (phi) in the 5.0 Hz-0.1 Hz frequency range, the equivalent series resistance (R-s) and the equivalent series capacitance (C-s) have been identified as suitable parameters for predicting the SOC values of the lithium-ion battery.

Journal ArticleDOI
TL;DR: In this article, the effects of surface roughness on electrical properties of a thin insulating film capacitor with one smooth electrode plate and one rough electrode plate are investigated, and the electrode plate roughness is described in terms of self-affine fractal scaling through the roughness exponent, the root-mean square (rms) roughness amplitude w and the correlation length.
Abstract: Effects of surface roughness on electrical properties of a thin insulating film capacitor with one smooth electrode plate and one rough electrode plate are investigated. The electrode plate roughness is described in terms of self-affine fractal scaling through the roughness exponent \ensuremath{\alpha}, the root-mean square (rms) roughness amplitude w, and the correlation length \ensuremath{\xi}. The electric field, capacitance, and leakage current show similar qualitative changes with the roughness parameters: they all increase as w increases, and also increase as either \ensuremath{\xi} or \ensuremath{\alpha} decreases.

Patent
15 Oct 1999
TL;DR: In this paper, a voltage tunable dielectric varactor is described, where the first and second electrodes are separated to form a gap there between the input and output, and a bias voltage applied to the electrodes changes the capacitance of the varactor between the inputs and outputs.
Abstract: A voltage tunable dielectric varactor includes a substrate having a low dielectric constant and having generally planar surface, a tunable ferroelectric layer positioned on the generally planar surface of the substrate, and first and second electrodes positioned on a surface of the tunable ferroelectric layer opposite the generally planar surface of the substrate. The first and second electrodes are separated to form a gap therebetween. The varactor includes an input for receiving a radio frequency signal and an output for delivering the radio frequency signal. A bias voltage applied to the electrodes changes the capacitance of the varactor between the input and output thereof. Phase shifters and filters that include the varactor are also described.

Patent
TL;DR: In this paper, the authors describe a method for obtaining pressure data using a body implantable pressure sensor, which includes a measurement capacitor which is responsive to pressure changes of a body fluid.
Abstract: An apparatus and method for obtaining pressure data using a body implantable pressure sensor includes a measurement capacitor which is responsive to pressure changes of a body fluid. Non-constant, multiple current source charging of the measurement capacitor provides for a significant increase in sensitivity to conditions of pressure of a body fluid. Pressure data is obtained by charging the measurement capacitor at a first charge rate during a first charge period of an integration cycle and, during a second charge period of the integration cycle, charging the measurement capacitor at a second charge rate. The first charge rate is preferably greater than the second charge rate. The duration of the first and second charge periods may be varied. A signal indicative of a pressure change of a body fluid imparted to the measurement capacitor is produced by the pressure sensor. The signal may be a signal indicative of a change in a time of integration. The signal, indicative of a time of integration, has a sensitivity to pressure changes which is greater than a mechanical capacitive sensitivity of the measurement capacitor to such pressure changes. The signal may alternatively be a signal indicative of a change in capacitance of the measurement capacitor, such as a voltage signal, or a signal having a duty cycle indicative of the pressure change. The pressure sensor may be implemented in a pacemaker, a pacemaker/cardioverter/defibrillator (PCD) or a hemodynamic monitor.

Journal ArticleDOI
C.T. Black1, J.J. Welser1
TL;DR: In this article, a simple, semiclassical model of an idealized capacitor is used to estimate the capacitance correction due to the distribution of displacement charge in the metal electrodes, which contributes to the universally seen decrease in measured dielectric constant with capacitor film thickness.
Abstract: A consequence of the finite electronic screening length in metals is that electric fields penetrate short distances into the metal surface. Using a simple, semiclassical model of an idealized capacitor, we estimate the capacitance correction due to the distribution of displacement charge in the metal electrodes. We compare our result with experimental data from thin-film high-dielectric-constant capacitors, which are currently leading contenders for use in future high-density memory applications. This intrinsic mechanism contributes to the universally-seen decrease in measured dielectric constant with capacitor film thickness.

Journal ArticleDOI
TL;DR: In this article, the principle of charge transference is used to create an extremely sensitive and stable device with unique properties that transcend those of more pedestrian capacitance sensors, known as charge transfer sensors.
Abstract: While the transference of charge is an essential aspect of every capacitance sensor, a relatively new form of sensor makes overt use of the principle of charge conservation first deduced by Watson in the 1740s. Updated to use a microcontroller, mosfet switches, fet‐input opamps and band gap references, the principle of charge transference can be used to create an extremely sensitive and stable device with unique properties that transcend those of more pedestrian capacitance sensors. Also known as “QT” sensors, charge transfer sensors can have a dynamic range spanning many decades with noise floors in the sub‐femtofarad regime, allowing differential resolutions of mere fractions of a femtofarad. Such sensors are proving to have unique applications considered heretofore impossible, while also proving themselves as replacements for much more expensive sensing systems using photoelectric, acoustic, RF, and optical imaging techniques.

Journal ArticleDOI
TL;DR: In this article, a detailed two-dimensional (2D) electromechanical simulation of polysilicon beams fabricated in the multiuser MEMS process (MUMPs) is performed, with an emphasis on the behavior when the beam is in contact with an underlying silicon nitride dielectric layer.
Abstract: Electrostatically actuated polysilicon beams fabricated in the multiuser MEMS process (MUMPs) are studied, with an emphasis on the behavior when the beam is in contact with an underlying silicon nitride dielectric layer. Detailed two-dimensional (2-D) electromechanical simulations, including the mechanical effects of stepups, stress-stiffening and contact, as well as the electrical effects of fringing fields and finite beam thickness, are performed. Comparisons are made to quasi-2-D and three-dimensional simulations. Pull-in voltage and capacitance-voltage measurements together with 2-D simulations are used to extract material properties. The electromechanical system is used to monitor charge buildup in the nitride which is modeled by a charge trapping model. Surface effects are included in the simulation using a compressible-contact-surface model. Monte Carlo simulations reveal the limits of simulation accuracy due to the limited resolution of input parameters.

Patent
13 Jul 1999
TL;DR: In this paper, the capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of a gate electrode above the source and drain regions.
Abstract: The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Journal ArticleDOI
TL;DR: In this article, an RF MEMs microelectromechanical system variable capacitor has been demonstrated with a 22:1 tuning range, tuning from 1.5 to 33.2 pF of capacitance.
Abstract: () ABSTRACT: An RF MEMs microelectromechanical system variable capacitor has been demonstrated with a 22:1 tuning range, tuning from 1.5 to 33.2 pF of capacitance. This capacitor was constructed using bistable MEMs membrane capacitors with individual tuning ranges of 70:1 to 100:1, control voltages in the 30-55 V range, switching speeds less than 10 mS, and operating frequencies as high as 40 GHz. These devices may eventually provide a viable alternative to electronic varactors with improved tuning range and lower loss. Q 1999 John Wiley & Sons, Inc. Int J RF and Microwave CAE 9: 362)374, 1999.

01 Jan 1999
TL;DR: Posey and Morozumi as mentioned in this paper developed a relationship between the physical properties of the cell components and the energy and power density of the device, and developed an electroanalytical tool to probe fundamental properties of new materials in advanced devices.
Abstract: Due to the high-rate capability of electrochemical capacitors (EC), they are considered excellent candidates for use in high-power applications such as load leveling the power sources in electric vehicles. 1-3 Electrochemical capacitors having large capacitance per gram of active material are of two types, 1 (i) double-layer capacitors and (ii) pseudocapacitors. The energy in the former device is stored across the double layer formed at the interface between an electronically conducting substrate and the electrolyte. The capacitance of a double layer is typically in the range of 10 to 40 mF per cm 2 of surface area. 4 Therefore, to achieve the requisite energy densities, highsurface-area materials such as activated carbon are used. 5 In contrast, pseudocapacitors are based on faradaic reactions that exhibit a current-voltage response similar to a capacitor. Examples of systems that exhibit faradaic pseudocapacitance are underpotential deposition of H or Pb in monolayers on noble metals and redox reactions of microporous transition metal hydrous oxides such as RuO 2 1 and NiO. 6,7 To produce cost-effective materials with the desired electrochemical performance, a systematic approach is needed to relate process conditions to electrochemical characteristics. Such a systematic approach can be aided by mathematical models for understanding the relationship between electrode structure (e.g., porosity, capacitance, surface area, and thickness) and performance (e.g., energy and power density). The objective of this paper is to use mathematical models to (i) develop a relationship between the physical properties of the cell components and the energy and power density of the device; ( ii) gauge the importance of thermal effects on the performance of these devices; and (iii) develop an electroanalytical tool to probe fundamental properties of new materials in advanced devices. Tasks (i) and (ii) were achieved by solving the governing equation under constant-current operation, while task ( iii) was achieved by simulating electrochemical impedance spectroscopy. This paper modifies the constant-current model developed by Farahmandi 8 for calculating the energy and power densities of the cell as a function of design parameters and operating conditions. The model has also been used to simulate the temperature rise in the cell during constant-current cycling. There are numerous models dealing with the double-layer formation in porous electrodes in the literature. These models can be divided into two categories: (i) models used to simulate the charging of the double layer 9-13 and (ii) models used to simulate the performance of electrochemical capacitors. 8,14,15 Posey and Morozumi 9

Journal ArticleDOI
TL;DR: In this paper, the authors used CM and partial capacitance techniques for analytical evaluation of charge/current and electric-and magnetic-field distributions in a multilayered substrate coplanar waveguide (CPW) in the quasi-TEM approximation.
Abstract: Conformal mapping (CM) and partial capacitance techniques are used for analytical evaluation of charge/current and electric- and magnetic-field distributions in a multilayered substrate coplanar waveguide (CPW) in the quasi-TEM approximation. The results, compared with finite-element method simulations, show that the magnetic wall assumed at the dielectric-dielectric interfaces in CM is a good approximation for many practical cases. The method is applied to a CPW with a thin ferroelectric film used in tunable microwave devices.

Patent
20 Aug 1999
TL;DR: In this paper, a forward-reverse crosstalk compensation method is provided for compensating capacitance/inductance on a printed circuit board of a connector, which includes a forward compensation process and a reverse compensation process.
Abstract: A forward-reverse crosstalk compensation method is provided for compensating capacitance/inductance on a printed circuit board of a connector. The method includes a forward compensation process and a reverse compensation process. The forward compensation process compensates the unbalanced capacitance in the plug of the connector by using the parallel conductive lines or wires. The reverse compensation process can be used to compensate the unbalance capacitance/inductance caused by the forward compensations in the same pair combination of the connector. In both forward compensation and reverse compensation processes, electro-magnetic fields, such as capacitors, can be formed to balance the capacitance/inductance on the printed circuit board of the connector.

Journal ArticleDOI
TL;DR: In this paper, double-layer capacitance is introduced in both the negative electrode and the positive electrode, and simulation results on the effect of short-time pulses passed through the cell are presented.
Abstract: The addition of double‐layer capacitance into a mathematical model of a dual lithium ion insertion cell is investigated. Double‐layer capacitance is introduced in both the negative electrode and the positive electrode. For the purposes of this paper, a |propylene carbonate + 1 M cell is used for the collection of simulation results. Simulation results on the effect of short‐time pulses passed through the cell are presented. Differences in the transient potential response in the negative and positive electrodes at short times are compared in cells with and without double‐layer capacitance using both linear and Butler‐Volmer kinetics. Comparisons are made between an electrode with a resistive film and one without and between situations with small and large rates of change of the open‐circuit potential with state of charge. A simpler resistive‐capacitive model is developed which clarifies many features of the modified behavior due to the capacitance but without simultaneously dealing with the discharge of the active material and concentration gradients. © 1999 The Electrochemical Society. All rights reserved.

Patent
31 Aug 1999
TL;DR: In this paper, a multi-port variable capacitor is described, where a movable plate is suspended above at least a first and a second, fixed, electrically-isolated electrode.
Abstract: An article comprising a multi-port variable capacitor is disclosed. In one embodiment, a movable plate is suspended above at least a first and a second, fixed, electrically-isolated electrode. The first electrode is electrically connected to a bias supply, and the second electrode is electrically connected to an AC signal-carrying line. As bias is applied across the first electrode and the movable plate, an electrostatic attraction is developed therebetween that causes the movable plate to move downwardly towards the first electrode. The capacitance of the variable capacitor increases as the separation distance between the movable plate and the fixed electrodes decreases. Unlike conventional variable capacitors, in the present multi-port variable capacitors, the bias (delivered via the first electrode) and the signal (delivered via the second electrode) are electrically isolated from one another. As such, the bias (DC) and signal (AC) paths are advantageously electrically isolated. In an additional embodiment, the movable plate of the present variable capacitor is operable to tilt. The ability to tilt provides additional “signal processing” (i.e., logic) capabilities to the present multi-port variable capacitors. In additional embodiments, an article in accordance with the present teachings comprises a monolithically-integrable, tunable LC circuit, and a variable-frequency oscillator. In such LC circuits and oscillators, the multi-port variable capacitor described herein is used to tune the resonant frequency of the circuit.

Journal ArticleDOI
TL;DR: Theoretical analysis and numerical calculations for ultra-high-speed traveling-wave electroabsorption modulators (TW-EAM's), including effects of velocity mismatch, impedance mismatch, and microwave attenuation, are presented in this article.
Abstract: Theoretical analysis and numerical calculations are presented for ultrahigh-speed (>50 GHz) traveling-wave electroabsorption modulators (TW-EAM's), including effects of velocity mismatch, impedance mismatch, and microwave attenuation. A quasi-static equivalent circuit model is used to examine the TW-EAM microwave properties, including the effect of photocurrent. Due to the optical propagation loss of the waveguide, the TW-EAM waveguide length for maximum RF link gain is currently limited to 200-300 /spl mu/m. The discussion indicates that the carrier transit time in the intrinsic layer may not severely limit the TW-EAM bandwidth. Three TW-EAM design approaches are discussed: low-impedance matching; reducing the waveguide capacitance; and distributing the modulation region.