Showing papers on "Chip published in 2001"

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

A 10000 frames/s CMOS digital pixel sensor

Abstract: A 352/spl times/288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-/spl mu/m CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4/spl times/9.4 /spl mu/m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 /spl mu/V/e/sup -/. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.

Design and results from the APV25, a deep sub-micron CMOS front-end chip for the CMS tracker

Abstract: The APV25 is a 128-channel analogue pipeline chip for the readout of silicon microstrip detectors in the CMS tracker at the LHC. Each channel comprises a low noise amplifier, a 192-cell analogue pipeline and a deconvolution readout circuit. Output data are transmitted on a single differential current output via an analogue multiplexer. The chip is fabricated in a standard 0.25 μm CMOS process to take advantage of the radiation tolerance, lower noise and power, and high circuit density. Experimental characterisation of this circuit shows full functionality and good performance both in pre- and post-irradiation (20 Mrad) conditions. The measured noise is significantly reduced compared to earlier APV versions. A description of the design and results from measurements prior to irradiation are presented.

RF/wireless interconnect for inter- and intra-chip communications

Abstract: Recent studies showed that conventional approaches being used to solve problems imposed by hard-wired metal interconnects will eventually encounter fundamental limits and may impede the advance of future ultralarge-scale integrated circuits (ULSls). To surpass these fundamental limits, we introduce a novel RF/wireless interconnect concept for future inter- and intra-ULSI communications. Unlike the traditional "passive" metal interconnect, the "active" RF/wireless interconnect is based on low loss and dispersion-free microwave signal transmission, near-field capacitive coupling, and modem multiple-access algorithms. In this paper we address issues relevant to the signal channeling of the RF/wireless interconnect and discuss its advantages in speed, signal integrity, and channel reconfiguration. The electronic overhead required in the RF/wireless-interconnect system and its compatibility with the future ULSI and MCM (multi-chip-module) will be discussed as well.

Noninvasive neuroelectronic interfacing with synaptically connected snail neurons immobilized on a semiconductor chip

Abstract: A hybrid circuit of a semiconductor chip and synaptically connected neurons was implemented and characterized. Individual nerve cells from the snail Lymnaea stagnalis were immobilized on a silicon chip by microscopic picket fences of polyimide. The cells formed a network with electrical synapses after outgrowth in brain conditioned medium. Pairs of neurons were electronically interfaced for noninvasive stimulation and recording. Voltage pulses were applied to a capacitive stimulator on the chip to excite the attached neuron. Signals were transmitted in the neuronal net and elicited an action potential in a second neuron. The postsynaptic excitation modulated the current of a transistor on the chip. The implementation of the silicon-neuron-neuron-silicon circuit constitutes a proof-of-principle experiment for the development of neuroelectronic systems to be used in studies on neuronal signal processing, neurocomputation, and neuroprosthetics.

Low-pin-count chip package and manufacturing method thereof

Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated by a package body in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a T-shaped profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.

Radio frequency identification and the electronic product code

Abstract: Remotely scannable IC chips that can access vast amounts of constantly updated information and cost only pennies could be close to reality. New technological developments and a decline in chip cost hold the promise of an automatic data and identification system that uses the Internet.

Light source using semiconductor devices mounted on a heat sink

Abstract: A semiconductor light source for illuminating a physical space has been invented. In various embodiments of the invention, a semiconductor such as and LED chip, laser chip, LED chip array, laser array, an array of chips, or a VCSEL chip is mounted on a heat sink. The heat sink may have multiple panels for mounting chips in various orientations. The chips may be mounted directly to a primary heat sink which is in turn mounted to a multi-panel secondary heat sink. A TE cooler and air circulation may be provided to enhance heat dissipation. An AC/DC converter may be included in the light source fitting.

A comparative study of the performance of seven- and 63-chip optical code-division multiple-access encoders and decoders based on superstructured fiber Bragg gratings

Abstract: We report a range of elementary optical coding and decoding experiments employing superstructured fiber Bragg grating (SSFBG) components: first, we perform a comparative study of the relative merits of bipolar and unipolar coding: decoding schemes and show that the SSFBG approach allows high-quality unipolar and bipolar coding. A performance close to that-theoretically predicted for seven-chip, 160-Gchip/s M-sequence codes is obtained. Second, we report the fabrication and performance of 63-chip, 160-Gchip/s, bipolar Gold sequence grating pairs. These codes are at least eight times longer than those generated by any other scheme based on fiber grating technology so far reported. Last, we describe a range of transmission system experiments for both the seven- and 63-bit bipolar grating pairs. Error-free performance is obtained over transmission distances of /spl sim/25 km of standard fiber. In addition, we have demonstrated error-free performance under multiuser operation (two simultaneous users). Our results highlight the precision and flexibility of our particular grating writing process and show that SSFBG technology represents a promising technology not just for optical code division multiple access (OCDMA) but also for an extended range of other pulse-shaping optical processing applications.

Successive interference cancellation with SISO decoding and EM channel estimation

Abstract: We derive a low-complexity receiver scheme for joint multiuser decoding and parameter estimation of code division multiple access signals. The resulting receiver processes the users serially and iteratively and makes use of soft-in soft-out single-user decoders, of soft interference cancellation and of expectation-maximization parameter estimation as the main building blocks. Computer simulations show that the proposed receiver achieves near single-user performance at very high channel load (number of users per chip) and outperforms conventional schemes with similar complexity.

Current Status of Research and Development for Three-Dimensional Chip Stack Technology

Abstract: The national project of "Ultra High-Density Electronic System Integration" was initiated in 1999. This is the first project to focus on a niche area between electronic devices and systems. It aims to develop technologies for overcoming the problems in terms of performance of electronic systems. Three-dimensional (3D) LSI chip stacking, optoelectronics hybrid integration, and optimum circuit design are the technology categories. For the 3D stacking technology, a chip-based stacking technology is under extensive development that includes wafer preparation for chip stacking, wafer thinning, chip stacking, and inspection and testing. In this paper, the current development status of the 3D stacking technology, called V-STACK technology, is introduced.

A programmable intraocular CMOS pressure sensor system implant

Abstract: We present a programmable intraocular pressure sensor system implant integrated on a single CMOS chip. It contains an on-chip micromechanical pressure sensor array, a temperature sensor, readout and calibration electronics, a /spl mu/C-based digital control unit, and an RF transponder. The transponder enables wireless data transmission and wireless power reception, thus making batteryless operation feasible. The chip has been fabricated in a 1.2-/spl mu/m n-well CMOS process complemented by additional processing steps.

Light-emitting device

Abstract: PROBLEM TO BE SOLVED: To provide a light-emitting device for improving directivity and brightness. SOLUTION: In a light-emitting device 1, where an LED chip 4 is arranged on the surface of a circuit substrate 2 whose surface is flat and at the same time, is molded by a light-transmitting resin 6, a thick-film reflection covering 5 is formed in contact with the light-transmitting resin 6 on the surface of the substrate 2, so that the LED chip 4 is surrounded.

A self-calibrating single-chip CMOS camera with logarithmic response

Abstract: A high-dynamic-range CMOS image sensor consisting of nonintegrating, continuously working photoreceptors with logarithmic response is presented. The nonuniformity problem caused by the device-to-device variations is greatly reduced by an implemented analog self-calibration. After performing this calibration, the remaining fixed pattern noise amounts to 3.8% (RMS) of an intensity decade at a uniform illumination of 1 W/m/sup 2/. The sensor provides a resolution of 384/spl times/288 pixels and a dynamic range of 6 decades in the intensity region from 3 mW/m/sup 2/ to 3 kW/m/sup 2/. It contains all components required for operating as a camera-on-a-chip. The image data can be read out either via a single analog line (video standard) or via a digital interface after undergoing an analog-to-digital conversion on the chip. Additional features like automatic exposure control, averaging of adjacent pixels, and digital zoom have been implemented, making the sensor suitable for a wide field of applications.

Semiconductor package with singulation crease

Abstract: An integrated circuit chip package comprising a lead frame having an integrated circuit die electrically connected thereto. Partially encapsulating the lead frame and the integrated circuit die is a package body. The package body includes the central portion which is circumvented by a peripheral portion defining opposed top and bottom surfaces. Disposed in at least one of the top and bottom surfaces of the peripheral portion of the package body is a singulation crease. The singulation crease, which is formed in the package body during its molding process, is used to provide a stress concentration line which reduces stress along the edge of the chip package and avoids chipping and cracking problems during the punch singulation process used to complete the manufacture of the same.

Shared channel structure, ARQ systems and methods

Abstract: A forward link design is provided employing CDMA (code division multiple access) technologies in which time division multiplexing is employed between data and control information on the forward link to service multiple users per slot Another forward link design employing CDMA (code division multiple access) technologies is provided in which code division multiplexing between data and control information is employed on the forward link to service multiple users per slot, which is preferably backwards compatible with legacy standards such as IS2000A A reverse link design is also provided

An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver

Abstract: A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility Their design highlights the tradeoff between performance, lifetime, cost, and power consumption Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation) These considerations are illustrated by the design of a prototype receiver chip realized in a standard 05-/spl mu/m digital CMOS process with 06-V threshold voltage The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode It achieves a -95 dBm sensitivity for a data rate of 24 kb/s

Multichip semiconductor device and memory card

Abstract: A plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device. In each of the semiconductor chips, an optional circuit is formed. In the optional circuit, fuses corresponding to the stacked-stage number of each chip are formed and the fuses are selectively cut off so as to permit each chip to individually receive a chip control signal.

Single chip device for voice communications

Abstract: The present invention is a chip for use in a voice communication device. The chip provides for both bone conduction sensing and air conduction sensing. The chip includes a bone conduction sensing pattern disposed within the chip and a microphone sensing pattern disposed within the chip. In addition, the chip can optionally include an integrated circuit portion interconnected to the bone conduction sensing pattern and the microphone sensing pattern. The pattern can be of a piezoelectric polymer, the patterns overlaying the substrate. Preferably, the bone conduction sensing pattern and the microphone sensing pattern are placed on opposite ends of the chip.

Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

Abstract: The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A reimplementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath.

Chip to chip interface for interconnecting chips

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

Micropower peak strain detection system for remote interrogation

Abstract: A sensing device includes an RFID chip and a differential variable reluctance transducer (DVRT) sensor that can be read remotely with electromagnetic power provided to the device from a remote reader. The ac signal provided to the device by inductance is used for powering the RFID chip and exciting the sensor. Data read from the sensor can also be transmitted back to the reader using the power provided by the reader. The sensor circuit uses a lower amount of current than the RFID chip, so it does not contribute appreciably to device power requirements.

A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller

Abstract: This paper describes a new generation of contactless smart card chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller. Beyond the contactless smart card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-/spl mu/m technology from STMicroelectronics.

Physical design of a fourth-generation POWER GHz microprocessor

Abstract: The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.

Method and apparatus for transmitter noise cancellation in an RF communications system

Abstract: A method and apparatus is provided for reducing or eliminating the transmitter signal leakage, i.e., transmitter noise, in the receiver path of an RF communications system operating in full duplex mode. In an embodiment of the present invention, a noise cancellation loop produces an estimated transmitter signal leakage and cancels it from the receiver path to produce a received signal with little or no transmitter noise. Some of the advantages are that there is significant improvement in the isolation between the transmitter/receiver circuits, the size of the RF communications circuitry may be reduced, and the RF transmit module along with the RF receive module may be incorporated into a single RF IC chip.

Stacked type semiconductor device

Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.

Method of manufacturing semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that allows to eliminate a dicing tape and a push-up pin or the like, which are conventionally used, in a series of semiconductor device manufacturing steps. SOLUTION: A first manufacturing method for a semiconductor device is composed of a step for sticking a surface protection sheet on a circuit face of a semiconductor wafer having a surface formed with a circuit, a step for grinding a rear face of the wafer, a step for dividing the wafer into individual pieces by performing full-cut dicing of the wafer from the ground-face side for each circuit while the wafer is being supported by the surface protection sheet, a step for suckingly fixing the wafer to a suction table, which has a plurality of independently-controllable suction parts so as to suckingly fix the wafer as a whole, while arranging the ground face of the wafer oppositely to the suction table, a step for exfoliating and removing the surface protection sheet from the wafer divided into individual pieces, a step for partially releasing or weakening a suction force by controlling each suction part of the suction table so as to pick up the wafer divided into individual pieces for each chip, and a step for bonding each chip to a semiconductor substrate. COPYRIGHT: (C)2008,JPO&INPIT

Chip socket assembly and chip file assembly for semiconductor chips

Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.

256-channel bidirectional optical interconnect using VCSELs and photodiodes on CMOS

Abstract: Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 035-/spl mu/m complementary metal-oxide-semiconductor (CMOS) chip The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate