Showing papers on "Electronic packaging published in 2019"

Recent advances in nano-materials for packaging of electronic devices

Abstract: In recent years, Moore’s law had a remarkable effect on predicting the development of semiconductor technology. As the size of devices shrinks to micro scale or nano scale, Intel’s newest 10-nm logic technology is scheduled to start product shipments before the end of 2017. Moore’s law will not die out, as the research scale reaches the atomic scale, “new devices” and new interconnection methods are urgently needed. In this paper, based on emerging interconnection requirement, the contribution to the advanced electronic packaging containing novel nano-materials, such as the carbon nanotubes, nanoparticles sintering, interconnection of nano-solder, nano-silver and surface plasma nano-welding are discussed. For the next 5–10 years, two new types of interconnect solutions are gaining attentions: solder joint alternatives and Cu electrode alternatives. The former uses new materials such as graphene, carbon nanotubes and nanowires to replace traditional solder joints. The latter uses optical media to replace the traditional Cu metal. In general, advanced materials will make more and more outstanding contributions in the development of electronic packaging in the next 10–20 years.

Segregated double network enabled effective electromagnetic shielding composites with extraordinary electrical insulation and thermal conductivity

Abstract: Miniaturization and high frequency are two key features of the next generation electronic devices, thus advanced electronic packaging materials with high thermal conductivity and excellent electromagnetic shielding performance (EMI SE) are highly expected. This work presents poly (vinylidene fluoride)@multi-wall carbon nanotube/boron nitride (PVDF@MWCNT/BN) composites with effective EMI SE and satisfactory insulation and thermal conductivity through a tailor-made segregated double network. PVDF@MWCNT composite microspheres were fabricated as the thermal and electrical conductive micro-network, then another BN macro-network was further prepared to provide electrical insulation and further thermal conductivity enhancement. This so-called double segregated network of PVDF@MWCNT/BN composites shows a thermal conductivity of 0.83 W m−1 K−1, electron insulation of 8.33 × 10−14 S cm−1 and electromagnetic shielding of 8.68 dB at 8.2 GHz when loaded 5 wt% MWCNT and 40 wt% BN. The study sheds new lights on the development of special functional materials and the PVDF@MWCNT/BN composites are highly promising as a future electronic packaging material.

Experimental investigations into triplex hybrid process of GA-RDECDM during subtractive processing of MMC’s

Abstract: The use of Al-6063 SiCp metal matrix composites (MMCs) in electronic packaging applications, heat sinks for printed circuit boards and for microwave housings necessitates certain degree of machinin...

Moore’s Law for Packaging to Replace Moore’s Law for ICS

Abstract: This article proposes Moore’s Law for Packaging to replace Moore’s Law for ICs, as this is seen as coming to an end. Moore’s Law for ICs is about scaling transistors to ever smaller sizes, from node to node and interconnecting and integrating these to result in more transistors in smaller chips at lower cost from 300 mm wafers. As transistor scaling and integration comes to an end due to physical, material and electrical limitations, Moore’s Law for Packaging (MLP) can be viewed as interconnecting and integrating smaller chips with the highest transistor density with the highest performance at the lowest cost. Package or system scaling is proposed to be one and the same as the end goal of packaging is a system. Just as Moore’s Law has two components: number of transistors and cost of each transistor, Moore’s Law for Packaging is proposed to have two components as well: the number of interconnections or I/Os and the cost of each I/O. This article lays the ground work for Moore’s Law for Packaging by showing how I/Os have evolved from one package family node to the next, starting with <16 I/Os in 1960s to the current silicon interposers with about 200,000 I/Os. It proposes a variety of ways to extend Moore’s Law such as extending Si interposers and beyond, using glass in panel embedding. As Moore’s Law for Electronic Packaging comes to its own end, this article proposes 3D opto-electronic packaging as the next Moore’s Law for Packaging.

Epoxy Polymer Solder Pastes for Micro-Electronic Packaging Applications

Abstract: Epoxy solder pastes are widely used in microelectronic packaging for joining die, interconnects, screen displays and as a heat dissipaters. Due to their simplicity and high reliability in chip or package bonding, epoxy solder pastes have been recently paid great attention as a competitive bonding material. The epoxy-based pastes are composed of conducting fillers (solder powder, metallic particles) mixed with epoxy polymer. The bonded joint is robust and has a higher strength after the curing of the epoxy polymer during joining. The inclusion of epoxy as a matrix also alleviate the problem of short-circuiting caused by metallic whisker formation. In view of these advantages, epoxy solder is highly attractive amongst electronic packages and in automotive cars. In this review, we have summarized the background and recent developments in the field of epoxybased solder pastes for electronic and automotive interconnection. Further improvements to improve this technology is also discussed in detail.

Convergence and Validation in ParaPower: A Design Tool for Phase Change Materials in Electronics Packaging

Abstract: Integration of solid-liquid phase change materials (PCMs) into electronics packaging has demonstrated the potential to reduce the transient temperature rise of components that experience pulsed thermal loads. However, the impact on local temperature histories resulting from incorporating PCMs in different locations and configurations within an electronics package is not easy to analytically determine, due in large part to the non-linear response of PCMs to a transient heat load. ParaPower is a new parametric design tool to facilitate the design of electronics packages. The tool has the capability of easily incorporating arbitrarily located PCM volumes and evaluating their effect on temperature distributions within the electronics package as a function of time. This paper determines the spatial and temporal order of convergence for the reduced order phase-change thermal model which underlies ParaPower. The results are compared and validated against both an analytical solution and a higher-fidelity commercial finite element analysis (FEA) tool. This paper has shown the fast-solving methods used in the ParaPower tool give results with comparable accuracy to those obtained using high-fidelity commercial software. Reasonably good accuracy can be obtained with fairly large time steps and grid spacing allowing fast-solving design space exploration with this option to increase fidelity within the tool to obtain higher accuracy when necessary. This research quantifies the trade-off between time steps, grid size, and accuracy such that a useful balance can be obtained. Design tools, such as ParaPower, have the potential to significantly advance design theory to reduce size and cost as well as minimize the prevalence of overdesign.

A Novel Method for Embedding Semiconductor Dies within Textile Yarn to Create Electronic Textiles

Abstract: Electronic yarns (E-yarns) contain electronics fully incorporated into the yarn’s structure prior to textile or garment production. They consist of a conductive core made from a flexible, multi-strand copper wire onto which semiconductor dies or MEMS (microelectromechanical systems) are soldered. The device and solder joints are then encapsulated within a resin micro-pod, which is subsequently surrounded by a textile sheath, which also covers the copper wires. The encapsulation of semiconductor dies or MEMS devices within the resin polymer micro-pod is a critical component of the fabrication process, as the micro-pod protects the dies from mechanical and chemical stresses, and hermetically seals the device, which makes the E-yarn washable. The process of manufacturing E-yarns requires automation to increase production speeds and to ensure consistency of the micro-pod structure. The design and development of a semi-automated encapsulation unit used to fabricate the micro-pods is presented here. The micro-pods were made from a ultra-violet (UV) curable polymer resin. This work details the choice of machinery and methods to create a semi-automated encapsulation system in which incoming dies were detected then covered in resin micro-pods. The system detected incoming 0402 metric package dies with an accuracy of 87 to 98%.

A Review of Interface Microstructures in Electronic Packaging Applications: Soldering Technology

Abstract: This report examines the role of interfaces in electronic packaging applications with the focus placed on soldering technology. Materials and processes are described with respect to their roles on the performance and reliability of associated interfaces. The discussion will also include interface microstructures created by coatings and finishes that are frequently used in packaging applications. Numerous examples are cited to illustrate the importance of interfaces in physical and mechanical metallurgy as well as the engineering function of interconnections. Regardless of the specific application, interfaces are non-equilibrium structures, which has important ramifications for the long-term reliability of electronic packaging.

Novel Electronic Packaging Method for Functional Electronic Textiles

Abstract: A novel packaging method that enables the reliable mounting and protection of bare die within a textile yarn has been investigated. The reliability of electronic textiles is highly challenging given the flexibility of the fabric and the rigors of typical applications. Achieving reliable operation requires novel packaging approaches. In order to maximize the reliability and to minimize stresses in the electronic package, the die should be located as close as possible to the central axis of the overall assembly. The die is bonded to a bottom Kapton substrate that contains patterned conductive interconnects and bond pads forming the functional circuit. The circuit is protected by a molded Kapton film that has recesses formed where the die is located. This approach has been compared with three other traditional packaging technologies during washing, twisting, and cyclical bending tests. The novel electronic packaging method shows the best performance in all tests surviving up to 45 wash cycles.

Heat Transfer and Pressure Drop Performance of Additively Manufactured Polymer Heat Spreaders for Low-Weight Directed Cooling Integration in Power Electronics

Abstract: This study aims to provide an additive manufacturing-based pathway for addressing issues concerned with the reliability of high-density electronic packaging. It compares the performance of a non-metallic, additively manufactured heat spreader with that of a conventional cold plate. CFD software is first used to evaluate the heat spreaders with respect to cooling capability. Furthermore, the device is experimentally tested in a flow loop and its performance compared to that of the cold plate. Initial simulation results show the additively manufactured plastic heat sinks provide a uniform cooling profile and maintain lower maximum temperatures seen in the power module. Experimental results show a lower pressure drop seen is seen in the heat spreader over a wide range of flow rates. Moreover, the use of plastics shows a clear discount of EMI while keeping the material cost and the device weight at a reduced level.

Experimental Study on the Reliability of PBGA Electronic Packaging under Shock Loading

Abstract: Plastic Ball Grid Array (PBGA) one of the most important electronic packaging methods, is widely used in aeronautical industry field. According to the JEDEC standard, shock tests of PBGA assemblies are conducted under different loading conditions. Several important parameters, such as the fatigue life of PBGA assemblies, the relationship between solder joint positions and fatigue life, the relationship between strain energy density and fatigue life, are analyzed based on experiment results. The failure modes of PBGA assemblies are studied by optical microscope (OM). The results show that during the shock tests, the strains of the solder joints near the center of the specimen are larger than other positions, and these solder joints are prone to form micro cracks. With the increase of the shock times, these micro cracks extend rapidly which will eventually cause the failure of the PBGA electronic packaging.

Improved Thermal Conductivity and Mechanical Property of PTFE Reinforced with Al2O3

Abstract: To achieve polymer-based composites for electronic packaging with high thermal conductivity, Al2O3 nanoplatelets were introduced into polytetrafluoroethylene (PTFE) matrix via a cold pressing and s...

3D wafer level packaging technology based on the co-planar Au–Si bonding structure

Abstract: Driven by ever-growing demands on 3D integration, various state-of-the-art electronics packaging techniques have been developed. This study presents a novel and cost-efficient 3D wafer level packaging technology based on co-planar Au–Si bonding structures, whose two remarkable features are (1) eliminating the height difference derived from multi-layer metal interconnection lines crossing bonding rings by building co-planar bonding structures and (2) accomplishing vertical interconnections of low-resistivity Si column structures by forming Au–Si bonding ohmic contacts. In this paper, the packaging structure is interpreted by designs, fabrications and tests, in which the efficiency verification on co-planar bonding structures and vertical interconnections is concretely addressed. The performances on co-planar bonding structures have been revealed by 3D profiles of bonding surfaces, cross-sectional SEM images (the gap-free bonding layer) and tensile tests for Au–Si bonding strength. Besides, tests on leak rates of packaged chips indicate good packaging hermeticity. In terms of vertical interconnection properties, an in situ extracting method on the specific contact resistance (ρ c ) is also introduced to quantitatively appraise the quality of Au–Si ohmic contacts. Therefrom, the measured resistance of a vertical interconnection (~1 Ω) could be qualified for most devices' interconnection requirements. And further, the extracted ρ c values of 1.83–3.48 × 10−8 Ω m2 also imply forming of good ohmic contacts in Au–Si bonding. More importantly, being analogously conducted by any available eutectic bonding techniques, this 3D packaging method has inherently extensive application prospects.

Board-level vapor phase soldering (VPS) with different temperature and vacuum conditions

Abstract: Purpose Vapor phase soldering (VPS), also known as condense soldering, is capable of improving the mechanical reliability of solder joints in electronic packaging structures. The paper aims to discuss this issue. Design/methodology/approach In the present study, VPS is utilized to assemble two typical packaging types (i.e. ceramic column grid array (CCGA) and BGA) for electronic devices with lead-containing and lead-free solders. By applying the peak soldering temperatures of 215°C and 235°C with and without vacuum condition, the void formation and intermetallic compound (IMC) thickness are compared for different packaging structures with lead-containing and lead-free solder alloys. Findings It is found that at the soldering temperature of 215°C, CCGA under a vacuum condition has fewer voids but BGA without vacuum environment has fewer voids despite of the existence of lead in solder alloy. In light of contradictory phenomenon about void formation at 215°C, a similar CCGA device is soldered via VPS at the temperature of 235°C. Compared with the size of voids formed at 215°C, no obvious void is found for CCGA with vacuum at the soldering temperature of 235°C. No matter what soldering temperature and vacuum condition are applied, the IMC thickness of CCGA and BGA can satisfy the requirement of 1.0–3.0 µm. Therefore, it can be concluded that the soldering temperature of 235°C in vacuum is the optimal VPS condition for void elimination. In addition, shear tests at the rate of 10 mm/min are performed to examine the load resistance and potential failure mode. In terms of failure mode observed in shear tests, interfacial shear failure occurs between PCB and bulk solder and also within bulk solder for CCGA soldered at temperatures of 215°C and 235°C. This means that an acceptable thicker IMC thickness between CCGA solder and device provides greater interfacial strength between CCGA and device. Originality/value Due to its high I/O capacity and satisfactory reliability in electrical and thermal performance, CCGA electronic devices have been widely adopted in the military and aerospace fields. In the present study, the authors utilized VPS to assemble a typical type of CCGA with the control package of conventional BGA to investigate the relation between essential condition (i.e. soldering temperature and vacuum) to void formation.

Failure Life Prediction of Wafer Level Packaging using DoS with AI Technology

Abstract: In regard to the design of new electronic packaging structure, e.g., wafer level packaging (WLP), one needs to consider many design factors that could affect the reliability characteristics of electronic package. Before mass production, the electrical packaging has to pass the reliability test. Thermal cycling test (TCT) is one of the standard reliability tests and has been commonly used in electrical packaging industry. To ensure the new products pass the thermal cyclic test is the critical issue in the electronic packaging industry. To react to the rapid growth of electronic components, it is imperative to shorten the development time and cycles of electronic packaging, design-on-experiment (DoE) method is quite time consuming and very costly, finite element method (FEM) based design-on-simulation technology could be used as a feasible development methodology for the reliability assessment and reliability prediction of electronic package. After the FEM model, mechanics theory, simulation procedures and reliability behavior, etc. being verified by experiments, simulation can be treated the same as the experiment if simulation can consistently get the results that similar to experiment. Simulation can build a set of reliability results database of different geometric structures of the WLP and provided this database for machine learning. Machine learning is an automatic analysis method which could learn a regression model from the database for predicting reliability cycles of package instantly. In this paper, the thermal cycling test (TCT) reliability of different geometry structures of Wafer Level Packaging is discussed through verified simulation technology. The database generated by FEM simulation is analyzed by artificial neural network (ANN), the training result shown ANN can predict the reliability of unknown structure of WLCSP in an accurate range.

Effects of graphene oxide on the electromigration lifetime of lead-free solder joints

Abstract: Electromigration (EM) is the mass transport of atoms due to electron flow, which induces a disconnect in electronic packaging. Recently, EM has received growing attention because it occurs easily when the size of joints in electronic packaging is reduced for better integration. Many researchers tried to improve the EM properties of solder joints by adding minor elements or using composites. Some studies reported that adding graphene, which is widely researched in recent years, to electronic packaging could improve the EM property. However, there is a lack of research on the EM lifetime characteristics with other materials added to the solder, such as minor elements, composites, and graphene. In this study, the effect of graphene oxide (GO) powder in Sn–3.0Ag–0.5Cu Pb-free solder paste on the EM lifetime of the solder joint was investigated. Using the fabricated solder paste and a reflow process, the printed circuit board finished with organic solderability preservative on Cu pad and Ni/Au-finished ball grid array packages with solder balls were joined. Afterwards, EM tests were performed at an elevated temperature of 130 °C and a current density of 1.0 × 103 A/cm2. The EM lifetime increased as the amount of added GO powders increased. Notably, the addition of 0.2 wt% GO nearly doubled the EM lifetime in the solder joint compared to that without GO.

Advanced RF Packaging Technology Trends, from WLP and 3D Integration to 5G and Mmwave Applications

Abstract: In the last few years, radio frequency (RF) applications have driven the advanced electronics packaging market to encompass different sectors. With products such as Automotive Radar, High-End Smartphones or WiGig devices, the RF packaging market is expected to grow in every sector. Wafer-level packaging (WLP), 3D through-silicon vias (TSVs), SiPs (Systems-in-Packages), and electromagnetic interference (EMI) shielding are key enablers for heterogeneous integration in segments where RF devices require small form factors, high speed operation and a high degree of isolation. Also, cost efficiency is critical. Based on images extracted from physical analyses of several RF devices, we will demonstrate the present power of RF packaging solutions for manufacturers such as Qualcomm, Broadcom, and Skyworks, from the manufacturing cost to the functional integration. We will extract some clues for future fifth generation (5G) and millimeter wave (mmWave) applications. We will also present how these companies manage to provide highly integrated SiPs featuring several advanced packaging technologies cost-effectively. Finally, moving forward in 5G and mmWave applications, SiPs will get more complex to maintain high performance levels, with innovations like integrated EMI shielding and integrated passive devices. We will therefore introduce some key features, like advanced substrate technologies. These are also next generation technologies for 5G and mmWave systems.

Stress Strain Analysis on Stitch Bond of Cu-Al Wirebonds Using X-ray Micro-CT Technique

Abstract: Wire bonding is the primary mode of interconnect between chip and substrate in electronics packaging. Gold has been used as the traditional wirebond material for the last six-decades. Owing to the low cost and better properties of copper, including high thermal conductivity, high strength, low electrical and thermal resistivity, stability, the electronics industry is shifting away from use of gold wirebonding. Stitch Cu-bonds have been known to be a potential failure location. Methods are needed to accurately capture the stitch bond geometry and assess propensity for failure. Electronic components comprise many material-interfaces between EMC (Epoxy mold compound), wire bonds, aluminum pads, silver die, die attachment adhesive and lead frame. Making traditional CAD model, mesh and FE models for electronic packages is time-consuming. In addition, nominal modeled geometry may not include manufacturing variabilities from molding and bonding processes. In this paper, wirebond geometries have been modeled based on x-ray MicroCT data for QFN Cu-wirebond packages. Six-versions of QFN were created with six-different EMCs. QFNs were subjected to thermal cycling to assess the effect of molding compound on the wirebond failure distributions. All six EMCs have been analyzed to assess the effect of EMCs on the stresses at the internal package elements, interfaces including the wirebonds.

Shear properties of isotropic conductive adhesive joints under different loading rates

Abstract: Epoxy-based conductive adhesives have been widely used in the electronic field given the lead-free development of electronic packaging. The conductive adhesive joints must be subjected to shear loa...

Optimal Design of Three-Dimensional Heat Flow Structures for Power Electronics Applications

Abstract: Design optimization of a three-dimensional (3D) heat flow structure for power electronics gate drive circuit thermal management is described. Optimization methods are described in the creation of several structural concepts targeted toward simultaneous temperature reduction of multiple gate drive integrated circuit (IC) devices. Each heat flow path concept is intended for seamless integration based on power electronics packaging space constraints, while maintaining required electrical isolation. The design synthesis and fabrication of a select concept prototype is presented along with the development of an experimental test bench for thermal performance characterization. Experimental results indicate a significant 45 ∘C maximum temperature reduction for the gate drive IC devices in a laboratory environment, which translates to an estimated 41 °C maximum temperature reduction under high temperature (∼100 °C) ambient conditions. The technical approach and design strategy are applicable to future wide band-gap (WBG) electronics packaging applications, where enhanced 3D thermal routing is expected to be critical to maximizing volumetric power density.

Empirical Solutions and Reliability Assessment of Thermal Induced Creep Failure for Wafer Level Packaging

Abstract: The accelerated thermal cycling test (ATCT) is a method of testing the electronic packaging reliability characteristic. A component must pass this test before being launched into the market. According to many studies, under thermal loading, the excessive thermal strain and stress occur between the package and substrate because of the coefficient of thermal expansion mismatch, which damages the solder bump of electrical packaging. In the ATCT, −40° C to 125° C is the regular thermal range of packages tested. Furthermore, the homologous temperature exceeds one-third of the melting point (K) of solder, and one should consider the accumulation of creep strain and estimate the creep behavior during the loading procedure; however, the creep strain is very sensitive to mesh size in finite element simulation. Obtaining a stable and reliable creep stain for different packaging structures becomes a must for solder joint reliability assessment. In this paper, we study a feasible and fixed element size, which should be chosen carefully for the same type of electronic packaging structure, for example, wafer level packaging (WLP), as it can affect simulation results and cause the prediction of the packaging life cycle to deviate. In ATCT simulation, there is a big difference in reliability estimation for different element mesh size selection, even if all material properties and structures remain the same. It is essential to find an appropriate and fixed element size for packaging reliability prediction to yield precise and reliable simulation results. This paper aims to find an appropriate element mesh size that can consistently predict the reliability life of various WLPs in an accurate range, and the reliability results of different WLPs under the thermal cycling loading have been validated by experiments. Moreover, the simulation results are summarized by using the Anand and hyperbolic sine creep models with suitable empirical reliability assessment equations, and the results show both creep models can predict the reliability life of WLPs in an accurate range with appropriate mesh control.

Research on life evaluation method of solder joint based on eddy current pulse thermography.

Abstract: With the wide usage of electronic packaging technologies such as Ball Grid Array in electronic industry, it is necessary to maintain its quality in order to meet the demand of electronic products for function, integration, and size reduction. However, as the size of solder joints in such technology decreases, the solder joints are more and more prone to defects. To solve the life prediction problem of small-size packages having interconnections in the high-density chip, a method based on the eddy current pulsed thermography (ECPT) is put forward to study the remaining life prediction of solder joints. A 3D induction heating finite element model is established, by which the crack length of defect solder joints can be distinguished using temperature field. At the same time, the remaining life of defect solder joints can be characterized by the length of the crack. Furthermore, the experiments are carried out on solder joints whose diameter is 0.4 mm. Both simulation and experiment results verify that it is reliable and convenient to use 3D induction heating based temperature field from ECPT to evaluate the remaining life of cracks in solder joints.

Thermo-Mechanical Process Emulation and Sensitivity Analysis of Wafer Warpage after Reconstitution in Fan-out Packaging

Abstract: Wafer reconstitution fan-out is a vital process for serving as a buffer to decouple the processing developments between IC fabrication and electronics packaging. By this approach, the IC packaging is then independent from the chip processing. However, such a process brings numerous mechanical loadings during molding and curing phases. In this work, it is desired to examine the key factor of reconstituted wafer warpage by performing solid thermo-mechanical analyses. To have a deeper insight, simplified 2D and detailed 3D finite element analyses have been constructed to mimic the entire Recon process. Detail thermo-mechanical processing steps are then emulated by these finite element models. After model validation, systematic parametric studies are then performed to investigate the controlling factors for dominating the wafer warpage. The simulation results indicated that the thermal expansion coefficients and the Young’s modulus of molding compounds could be the dominated factor. By choosing compounds with more desirable above-mentioned mechanical properties, it is expected that a 20 to 30 percentage reduction of warpage can be achieved.

Thermal Buffering Effect of Phase Change Material on Press-pack IGBT during Power Pulse

Abstract: Managing transient temperature of power semiconductor devices induced by power pulses is a challenge to thermal design in power electronic packaging. Due to the limited thermal capacity, the extra heat generated by overload current cannot be absorbed immediately, leading to junction temperature rising beyond the limit and thermal breakdown of the device. Integrating phase change material (PCM) into the packed power devices can be effective to suppress the junction temperature surges by making use of the latent heat. In this paper, the PCM-integrated packaging of a press-pack IGBT device is proposed, and the thermal buffering effect of PCMs is analyzed using both finite element analyses and experiments. It is shown that as the dissipation of extra heat is absorbed by the PCM, the junction temperature rise is significantly reduced during power pulses. The proposed packaging structure contributes to improve the short-term overcurrent capability of press-pack IGBT-based devices and the corresponding gridconnected converters in many grid scenarios.

Compact terahertz detector based on lightweight 3D-printed lens packaging

Abstract: This Letter presents a compact and lightweight terahertz detector with a 3D-printed lens packaging, exhibiting a high responsivity between 1100 and 2190 V/W from 210 to 230 GHz. The detector is comprised of an antenna-coupled detector, a 3D-printed lens and a read-out circuit. The antenna-coupled detector with a GaAs Schottky diode is printed on a dielectric laminate. To extract the detected signal more efficiently within a smaller footprint, a pair of folded lines with high impedance are designed. Moreover, a 3D-printed nylon lens together with a back-shorting reflector is proposed for radiation gain enhancement and mechanical robustness. A maximum voltage responsivity Rv of 2190 V/W and a minimum noise equivalent power of 2.6 pW/√Hz are achieved at 223 GHz. The measured radiation patterns agree well with the simulated results.

Feasibility Studies and Advantages of Using Dual Fiber Array in Laser Ultrasonic Inspection of Electronic Chip Packages

Abstract: Fabrication and inspection techniques of electronic packages are two key factors influencing a chip’s success in post-Moore’s law era. As the electronic packaging industry rapidly evolves to cope with modern demands, a versatile inspection method for present and future packages is required. One approach is the development of a fiber array laser ultrasonic inspection system as presented in this paper. The new system uses two laser excitation points, allowing higher total energies to be delivered to the chip’s surface without exceeding the thermoelastic regime and causing damage. These beams induce strong ultrasonic waves, which can penetrate deeper and farther into and across a package. As a result, larger and thicker packages can be nondestructively inspected than was previously possible. Flip-chip ball grid array packages of size 52.5 mm $\times52.5$ mm from Cisco were evaluated using this system and compared against a single-beam system. Benefits of the new system include an increase in vibration amplitude due to high laser power, improved signal-to-noise ratio (SNR), an increase in resolution/sensitivity to measure microcracks, and high speed. The new dual-fiber-array system can administer 400-mW power safely, and as a result, the peak-to-peak amplitude of the generated ultrasound is three times that of ultrasound generated from a single laser beam. The SNR of 8:1 is achieved on the current Cisco package with double excitation point sources compared to the SNR of 1:1 that was obtained with a single excitation point source.