Showing papers on "Equivalent series resistance published in 1990"

1/f noise in MODFETs at low drain bias

Abstract: The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S/sub I//I/sup 2/ versus the effective gate voltage V/sub G/=V/sub GS/-V/sub off/ shows three regions which are explained. The observed dependencies are S/sub I//I/sup 2/ varies as V/sub G//sup m/ with the exponents m=-1, -3, 0 with increasing values of V/sub G/. The model explains m=-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V/sub G/ or V/sub GS/ equivalent to 0 is due to the dominant contribution of the series resistance. In the region at intermediate V/sub G/, m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance. >

Drastic reduction of series resistance in doped semiconductor distributed Bragg reflectors for surface-emitting lasers

Abstract: Modifications to reduce the series resistance in p‐type semiconductor distributed Bragg reflectors (DBR) consisting of ten pairs of quarter‐wavelength GaAs (high refractive index)/Al0.7Ga0.3As (low index) layers were made by inserting an intermediate Al0.35Ga0.65As layer or a 200 A superlattice of GaAs(10 A)/Al0.7Ga0.3As (10 A) at the GaAs/Al0.7Ga0.3As heterointerfaces. The specific DBR series resistance was reduced by two orders of magnitude to about 6.2×10−5 Ω cm2. These modifications did not alter the optical reflectivity and nearly identical reflection spectra were measured.

Anomalous inductive effect in selenium Schottky diodes

Abstract: A region of anomalous negative capacitance has been observed with forward bias in Se‐Tl Schottky evaporated layer structures. The effect, which is more prevalent in diodes with lower series resistance, is due to an inductive contribution to the impedance that is believed to arise from high‐level injection of minority electrons into the bulk selenium.

Output buffer with enhanced electrostatic discharge protection

Abstract: A CMOS output buffer is disclosed, which provides ESD protection by incorporating a low resistance path within the p-channel pull-up device. Output buffers according to the prior art can be damaged by ESD occurring at the output terminal having a positive polarity, as the drain-to-substrate diode of the pull-down transistor breaks down in the reverse-bias direction, especially when second breakdown occurs. The p-channel pull-up device, formed within an n-well, is fabricated to have n-type diffusions disposed near to the p-type drain diffusions. The distance between the n-type diffusion and the drain diffusions in the pull-up device reduces the series "on" resistance of the drain-to-n-well diode of the pull-up device, to a level which keeps the voltage at the output terminal below the reverse-bias breakdown voltage of the drain-to-substrate diode in the pull-down device. The pull-up device may be constructed in a ladder structure to facillitate the reduction of this resistance. A further embodiment of the invention is disclosed which provides the same protection to the n-channel pull-down device, by way of an n-well diode with low series resistance, for open-drain or other pull-up configurations.

Reliability analysis of GaAs/AlGaAs HBTs under forward current/temperature stress

Abstract: The reliability of GaAs/AlGaAs heterojunction bipolar transistors is investigated by accelerated life-testing of discrete devices under forward bias stress at elevated temperatures. The DC device characteristics are monitored to evaluate the effect of bias/temperature stress on a large number of devices fabricated on MBE (molecular beam epitaxy) grown material. The primary degradation observed in some devices is a reduction in the current gain which appears to be due to an electric field-aided diffusion of interstitial Be from the base into the base-emitter graded region. Other devices with optimal epitaxial material show stable current gain after DC bias stress at high temperature. Ohmic contact degradation, with or without bias, is also observed at the emitter contact, resulting in an increased emitter series resistance. >

Modelling the inductive behaviour of short-base p-n junction diodes at high forward bias

Abstract: The inductive nature of short-base p - n junction diodes at high forward bias is explained by means of a novel equivalent circuit featuring separate paths for charging currents and convection currents. As suggested by other authors, also conductivity modulation turns out to play a role. The general conclusion is, that the a.c. diode capacitance changes sign when the (modulated) total series resistance of the diode becomes equal to its differential resistance.

Investigation of GaAs Schottky barrier diodes in the THz range

Abstract: The properties of GaAs Schottky barrier diodes as video detectors and mixing elements were investigated in the frequency range from 0.8–2.5 THz. For the most sensitive diode, the video responsivity and system noise temperature were measured as a function of incident laser power. The highest video responsivity was 2,000 V/W at 214μm and 60 V/W at 118μm. For five diodes differing in doping, capacitance, series resistance and anode diameter, the system noise temperature was measured at 214μm and 118μm. The best single sideband (SSB) values are 12,300 K and 24,200 K at 214μm and 118μm, respectively. The system noise temperature versus frequency is given over the range from 0.5–3 THz for two specific diodes demonstrating that the sharpness of the I–V characteristics is only of secondary importance for mixer perfomance at such high frequencies.

Manufacture of semiconductor device

Abstract: PURPOSE:To eliminate the voltage dependency of the capacitance of a MIS capacitor and reduce the parasitic series resistance of electrodes substantially and obtain a MIS capacitor with a large capacitance by a method wherein two electrodes of the MIS capacitor are composed of metal films. CONSTITUTION:An aluminum film is formed on the field oxide film 2 of a silicon substrate 1 and etched to form a first aluminum electrode 3. Then an interlayer insulating film 5 is formed over the whole surface of the substrate and patterned to form apertures 9 at a capacitor forming part and a lead electrode forming part. A nitride film 6 is formed over the whole surface and etched to remove the film 6 except the part on the capacitor forming part. After a photoresist film 4B is removed, an aluminum film is formed and patterned to form a second aluminum electrode 7 and a lead electrode 8 on the capacitor part and the electrode part respectively. With this constitution, the voltage dependency of the capacitance can be eliminated and the parasitic series resistance of the electrodes can be reduced, so that a capacitor with a large capacitance can be obtained.

Continuous wave top surface emitting quantum well lasers using hybrid metal/semiconductor reflectors

Abstract: Continuous wave lasing at room temperature of vertical cavity top surface emitting quantum well lasers using hybrid metal/semiconductor reflectors is demonstrated. Semi-transparent metal films, about 350 A thick, are used with a reduced number of periods of distributed Bragg reflectors to form a hybrid top mirror with greatly reduced electrical resistance. Voltage at a threshold current of 11 mA is as low as 3.2 V and 100Ω differential series resistance is obtained with lO =m diameter devices. Improved uniformity and yield were obtained using silver/gold thin films deposited in-situ under ultra-high vacuum after molecular beam epitaxial growth of the semiconductor layers.

Low series resistance vertical‐cavity front‐surface‐emitting laser diode

Abstract: We have fabricated a front‐surface‐emitting laser diode (FSELD) using a technique which relies on a double ion implant of oxygen and beryllium. The laser had a low operating voltage at the lasing threshold, a low series resistance, and a relatively small threshold current of 6 mA for a 25‐μm‐diam device. The lasing wavelength was 971 nm and the spectral width above threshold was 5 A. Since the light comes from the front surface of the wafer, the fabrication technique described here for realizing a FSELD can be used for the fabrication of vertical‐cavity visible surface‐emitting lasers.

Method of making a high breakdown active device structure with low series resistance

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased inpurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer devices include insulated gate field effect transistors and bipolar devices and the four layer device is a semiconductor controlled rectifier (SCR).

Overcoming the problems in determination of solar cell series resistance and diode factor

Abstract: A theory has been developed to determine solar cell design parameters in the conventional solar cell equation using measured cell Isc, Imp, Vmp and Voc. The theory overcomes the problem of series resistance becoming negative. It is shown that the diode factor a indeed depends upon cell temperature. The theoretical predictions are in good agreement with experimental observations.

Method for forming capacitor using FET process and structure formed by same

Abstract: A polysilicon or equivalent plate, to be used as an upper plate of the capacitor, is first formed over an oxide layer grown on a substrate. The length of the upper plate is made shorter than gate lengths of MOS transistors formed with the same process so that, after dopants are deposited into exposed regions of the substrate on both sides of the plate in a manner identical to forming self-aligned source and drain regions of an MOS transistor, the dopants will side-diffuse during drive-in and the diffused regions will be closely separated or merged under the plate. The resulting capacitor structure has a more stable capacitance with varying V GS levels than MOS transistors merely connected and used as capacitors and has a lower series resistance.

Characterization and modeling of silicon metal‐oxide‐semiconductor transistors at liquid‐helium temperature: Influence of source‐drain series resistances

Abstract: An analysis of silicon metal‐oxide‐semiconductor (MOS) transistor operation at liquid‐helium temperature is presented. More specifically, analytical models providing the drain current and transconductance characteristics in the linear and nonohmic regions are established in the presence of source‐drain series resistances. These models, which rely on a specific mobility law for very low temperature, enable a good description of MOS transistor operation to be obtained. They permit the understanding and the prediction of the effects of source‐drain series resistance both in the linear and nonlinear regions. Furthermore, they allow a suitable parameter extraction method to be developed for the liquid‐helium temperature range. In addition, peculiarities of the drain voltage dependence of the mobility at low longitudinal electric field are also pointed out and empirically accounted for in the modeling of the output characteristics.

Integrated circuit containing bi-polar and complementary mos transistors on a common substrate and method for the manufacture thereof

Abstract: An integrated circuit containing bipolar and complementary MOS transistors wherein the base and emitter terminals of the bipolar transistor, as well as the gate electrodes of the MOS transistors, are composed of a silicide or of a double layer polysilicon silicide. The base and emitter terminals, as well as the gate electrodes, are arranged in one level of the circuit and there p + doping or, respectively, n + doping proceeds by ion implantation in the manufacture of the source/drain zones of the MOS transistors. As a result of the alignment independent spacing between the emitter and the base contact, the base series resistance is kept low and a reduction of the space requirement is achieved. Smaller emitter widths are possible by employing the polycide or silicide as diffusion source and as the terminal for the emitter. The size of the bipolar transistor is not limited by the metallization grid, since the silicide terminals can be contacted via the field oxide. The integrated semiconductor circuit is employed in VLSI circuits having high switching speeds.

Extended Goodman model for series resistance masking on bulky semiconductor junction capacitance

Abstract: The effect of series resistance on the apparent semiconductor junction capacitance C’ has been studied after Goodman [J. Appl. Phys. 34, 329 (1963)] in an attempt to explain the occurrence of minima in the apparent C’−2 vs voltage characteristics at high frequencies and for a large series resistance. A correction scheme has been formulated to convert C’−2 into the actual C−2 at any bias and frequency. The present model is consistent with the apparent capacitance behavior of a commercial Si Zener diode in series with a discrete resistor.

Deeply-grooved silicon concentrator solar cells for use with prismatic covers

Abstract: Advanced-design 22-sun silicon concentrator solar cells that are compatible with and complementary to Entech prismatic covers are based on a deep, V-grooved silicon structure which reduces the sensitivity to minority carrier diffusion length. Additional benefits of this 3-D structure are reduced front-surface reflectance, increased light absorption and trapping, enhanced carrier collection, and reduced base series resistance. Large-area (38-cm/sup 2/ aperture) devices produced from 1.25- Omega -cm solar-grade silicon have open-circuit voltages as high as 683 mV and currents over 29 A. Initially, performance was limited by series resistance of the front contact due to the wide (20-mil) gridline finger spacing required to match the prismatic covers. However, cells fabricated with a finer contact grid have fill-factors of up to 0.828 at the design-point concentration. >

A novel DC measurement method for the accurate extraction of bipolar resistive parasitics

Abstract: A novel DC method for determining the components of series resistance in bipolar transistors is presented. As a DC technique, it shows unprecedented accuracy as demonstrated by its application to both metal-contacted heterojunction transistors and more conventional bipolar junction transistors. The measurement error was minimized by using a single double-base Kelvin-tapped transistor to extract all components of series resistance. The present work indicates that past methods for calculating the bias dependence of series resistances in bipolar devices are incorrect. Therefore, a correct expression for the bias-dependent intrinsic base resistance is also presented. >

Ion implantation masking method and devices

Abstract: Semiconductor processing techniques and devices are provided using a partially opaque ion implantation mask to control the profile of active layers in microwave and millimeter wave monolithic integrated circuits. An N+ layer can be implanted before or after active layer formation. Selection of mask thickness enables control of active channel depth. Adjustment of gate to drain separation in MMIC FETs is also enabled, to control gate to drain voltage. Source to gate series resistance is also controlled. Multiple dielectric layers afford variable mask thicknesses to enable simultaneous formation of differing power level devices monolithically in the same substrate, including low noise high speed devices and power devices. The process and device structure provides enhanced yield, performance, uniformity and reliability.

Compositional Change of the Au–Cu2Te Contact for Thin-Film CdS/CdTe Solar Cells

Abstract: The stability of thin-film CdS/CdTe solar cells with evaporated Au–Cu2Te contacts to the CdTe film has been investigated. A decrease in conversion efficiency due to an increase in series resistance was observed in the solar cells stored in air at room temperature for 120 days. The increase in series resistance is caused by an increase in contact resistance resulting from the compositional change in the Au–Cu2Te contact to the CdTe film.

Equivalent series resistance-the fourth parameter for tantalum capacitors

Abstract: The author outlines the reasons behind the interest in ESR (equivalent series resistance) of surface mount devices and details the processing steps which affect the ESR of a tantalum capacitor. It is noted that the operating frequencies of products which use tantalum surface mount capacitors are continually increasing. These higher frequencies have resulted in ESR becoming a specified parameter in numerous user drawings, industry standards, and military specifications for tantalum chips. >

Analytical and graphical methods or determination of solar cell parameters and investigations of shadowing effect

Abstract: In actual solar cells, the main power loss is due to the effect of the internal series resistance and the shunt resistance of the solar cell. Two methods; mathematical and graphical, were used to determine these two resistances for an Iraqi monocrystalline solar cell (type AI-Mansour). The results show that both of the series resistance (0·09 Ω) and the shunt resistance (210 Ω) can usually be neglected in an array performance evaluation for systems which don't use concentration arrangements In addition to the series and shunt resistances computations, the analysis of the mismatching among solar cells as well as the power dissipation by shadowed or faulty cells for different module configurations are discussed in detail in this paper. As a result it was found that the maximum number of cells that can be safely series, parallel connected are 50 and 6 cells respectively.

Peeled film GaAs solar cells for space power

Abstract: Gallium arsenide (GaAs) peeled film solar cells were fabricated, by Organo-Metallic Vapor Phase Epitaxy (OMVPE), incorporating an aluminum arsenide (AlAs) parting layer between the device structure and the GaAs substrate. This layer was selectively removed by etching in dilute hydrofloric (HF) acid to release the epitaxial film. Test devices exhibit high series resistance due to insufficient back contact area. A new design is presented which uses a coverglass superstrate for structural support and incorporates a coplanar back contact design. Devices based on this design should have a specific power approaching 700 W/Kg.

High-frequency current-viewing resistor

Abstract: A current-viewing resistor for accurately measuring high-frequency currents, e.g. at radio frequencies, includes a first resistance connected in series with a first inductance, the series combination being connected in parallel with a series combination of a second resistance and a second inductance. The second resistance is relatively large as compared with the first resistance, and the second inductance is relatively large as compared with the first inductance. The ratio of the first resistance to the first inductance is substantially equal to the ratio of the second resistance to the second inductance. As a result, the voltage measured across the second resistance is substantially equal to the voltage across the first resistance, and the current through the first resistance is substantially equal to the current to be measured.

Effects of contact resistance on the performance of photovoltaic infrared detectors

Abstract: The effects of detector series resistance on the electrooptical performance of infrared detectors are calculated by means of a simple diode model with a parallel photocurrent source. Calculations are performed for a number of variables, and series resistance is shown to be an important parameter in the design of photovoltaic detectors because it can limit operation in high performance design applications.© (1990) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

An equivalent circuit model for transverse acoustoelectric voltage measurements in semiconductors

Abstract: Nondestructive measurements for semiconductor parameters can be performed by acoustoelectric interaction and Transverse Acoustoelectric Voltage (TAV) measurements on the separate-medium structure. In these measurements the coupling between the semiconductor and the surface acoustic wave and the coupling between the semiconductor and the ground path play a critical role. Due to the nonhomogeneous gap, the coupling capacitance between the ground path at the surface of the piezoelectric crystal and the semiconductor cannot be calculated and it cannot either be measured, because of the presence of parasitic elements, particularly a contact resistance on the rear contact and the probe capacitance to the case. On the other hand, knowledge of the coupling capacitance is critical in most measurements involving acoustoelectric interaction. In the present work the case of surface trap density measurement on the silicon-silicon dioxide interface is examined. A measurement procedure for the coupling capacitance per unit area is developed, based on measurements of the TAV rise time, which is shown to be a function of the unknown capacitance and of a series resistance composed of the internal resistance of the acoustoelectric source and of the parasitic contact resistance. Internal resistance is theoretically calculated with an analysis of the r.f. interaction in the semiconductor, the effect of the contact resistance is discriminated by comparison of its influence on the rise and fall time. TAV waveforms showing rise time different from fall time are presented, obtained with a new measurement structure using a tungsten point as rear contact. This phenomenon represents a verification of the equivalent circuit model and of the theory of the internal resistance. It is also used in the calculation procedure of the coupling capacitance.

Production of long pulse high magnetic fields using chemical double-layer capacitor banks

Abstract: The application of CDLs (chemical double-layer capacitors) for the production of high magnetic fields is described. From a knowledge of the internal parameters of the individual CDL units, scaling laws are developed which allow the specification of a capacitor bank which can produce an arbitrary magnetic field. Bank designs are presented using both commercially available and laboratory prototype units capable of producing fields greater than 1 T for several seconds. A laboratory unit was built which operated at a voltage of 21 V, had an equivalent series resistance (ESR) of approximately 7 m Omega , and a capacitance of about 30 F. In practice, the limiting field is governed by material parameters such as magnet wire size, dynamic stresses, and system heating which limits the current on the time scale for discharge of the bank. To test the scaling relations, a capacitor bank was constructed from commercially available products. Bank designs based on commercial products are contrasted with those which could be realized with laboratory prototypes. >

Ultrahigh frequency diode

Abstract: PURPOSE:To extremely reduce a high frequency resistance due to the skin effect and to improve the multiple variation efficiency by forming a groove extending from the surface of an n-type epitaxial layer at a high concentration semiconductor substrate around a rectifying junction. CONSTITUTION:A groove 9 so formed as to extend from the surface of an epitaxial layer 2 at a semiconductor substrate 1 is formed around a p-n junction 4, after a p type diffused layer 3 is formed on the layer 2. A high frequency current flows from the junction 4 along the surface of the junction 4 to the substrate 1 as designated by an arrow 8 by means of the skin effect. The length of the passage of the high frequency current is substantially equal to the thickness of the layer 2, and a series resistance can be remarkably reduced in the operating layer in high frequency.

A practical method for extracting impurity profiles and effective mobilities of MOSFET's with nonuniform channel doping

Abstract: Complete profiling of channel impurity concentration up to the surface is presented using Gaussians whose parameters are determined, giving optimum fits to the measured capacitance voltage (C-V) profiles. A rectangular capacitor with a large aspect ratio is found to be effective in reducing series resistance for accurate (C-V) measurements at high frequencies. Effective mobilities are extracted from practical MOSFETs based on numerical analysis of the field effects using the obtained profiles and compared to those for uniform doping. >