Showing papers on "Gate oxide published in 1994"

SiC devices: physics and numerical simulation

Abstract: The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n/sup -/-n/sup +/ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 /spl Omega/cm/sup 2/, while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4/spl times/10/sup 6/ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations. >

Self-aligned, split-gate EEPROM device

Abstract: An EEPROM device capable of operating with a single low-voltage power supply includes a control gate electrode (30) and a select gate electrode (14) overlying separate portions of a channel region (32). Electrical charge is stored in an ONO layer (20) overlying a portion of the channel region (32) and separating the control gate electrode (30) from the channel region (32). The memory device is programmed using source-side injection, where electrons traverse the channel region (32) and are injected into trapping sites (34) located within the silicon nitride layer (24) of the ONO layer (20). To provide the necessary field gradient within the channel region (32), the control gate electrode (30) is spaced apart from the source region (16) by the select gate electrode (14). In either of two embodiments, two layers of polysilicon are used to form the select gate electrode (14) and the control gate electrode (30). The second layer of polysilicon is formed as a sidewall spacer on the first layer of polysilicon. Accordingly, a high-density memory device is achieved.

Charge Damage Caused by Electron Shading Effect

Abstract: An antenna covered with photoresist patterns having high-aspect-ratio openings caused charge damage to the gate oxide in various processing plasmas. This damage increased with the pattern's aspect ratio, and occurred even when the test wafer was cut into chips about 5 mm square and mounted on a wafer with insulation. These results prove the electron shading model: the photoresist patterns shade the antenna from electrons of oblique incidence, resulting in local charging occurring without a wafer-scale voltage difference, which is essential for conventional charging. The damaging current from this mechanism increased by a factor of more than ten with a decrease in the gate oxide thickness only from 8 nm to 6 nm, implying that the degree of shading depends on the gate charging voltage. An improved model is proposed to accommodate this strong dependence.

Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps

Abstract: A sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions. The source/drain regions are formed by ion implantation using the expendable structure (diamond-like-carbon) as a mask. After the expendable structure has performed its further purpose of protecting the gate dielectric from contamination during the annealing cycle, the structure is easily removed by O 2 plasma and replaced by a conventional metal gate material.

A self-aligned dual-bit split gate (dsg) flash eeprom cell

Abstract: An EEPROM cell structure includes two floating gate transistors (20, 22) separated by a select gate transistor (24) with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor The floating gates (20B, 22B) of the two transistors are formed from a first polysilicon layer, the control gates (20C, 22C) of the two transistors are formed from a second polysilicon layer, and the select gate (24A) is formed from a third polysilicon layer The channel length (24G) of the select transistor is fully self-aligned to the floating gate transistors (20, 22) A word line (28) is formed over the control gates and forms the select gate The word line (28) runs generally perpendicular to bit lines (22A, 20A) which contact the drain regions of the two floating gate transistors Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure

Vertical insulated gate transistor and method of manufacture

Abstract: A vertical insulated gate transistor such as a UMOSFET is manufactured. A source region of first conductivity type is formed on the bottom surface of a substrate. A base region of second conductivity type is formed on the source region. A low-impurity-concentration drift region is formed on the base region. On the top surface of this multilayer structure, a truncated U groove is formed. A buried gate electrode is formed inside the truncated U groove. This structure is effective to reduce gate-drain capacitance Cgd, gate-source capacitance Cgs, and drain resistance r d , thereby realizing a high-frequency high-output device. A distance between the gate and the drain is determined in a self-aligning manner, so that a fine structure and a high-frequency operation are easily realized and production yield is improved.

Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films

Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a semiconductor film on a substrate, oxidizing a surface of said semiconductor film in an oxidizing atmosphere with said semiconductor film heated or irradiated with light, and further depositing an oxide film on the oxidized surface of the semiconductor film by PVD or CVD The first oxide film has a good interface condition with the semiconductor film and a characteristics of an insulated gate field effect transistor can be improved if the first oxide film and the second oxide film are used as a gate insulating film

Three-terminal gate-controlled semiconductor switching device with rectifying-gate

Abstract: A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET). To turn-on the device, the gate electrode is biased positive and an inversion layer channel of relatively low resistance is formed in the silicon active region. The channel electrically connects the source of the silicon carbide MESFET (or JFET) with the source of the silicon MOSFET to thereby turn-on the device when a positive drain bias is applied.

Metal‐oxide‐semiconductor field‐effect‐transistor substrate current during Fowler–Nordheim tunneling stress and silicon dioxide reliability

Abstract: The origin of the substrate current of a metal‐oxide‐semiconductor field‐effect transistor when the gate oxide undergoes Fowler–Nordheim stress is investigated. It is also shown that anode hole injection current predicts the breakdown of silicon dioxide between 25 and 130 A and 2.4 and 12 V. While the measured substrate current is entirely due to anode hole injection for oxides thicker than 55 A, tunneling by valence‐band electrons contributes to the substrate current in thinner oxides. Valence‐band electron tunneling current is shown to increase with oxide stressing similar to low‐voltage gate oxide leakage; apparently, both are enhanced by trap‐assisted tunneling. For oxides of thickness between 25 and 130 A, the theory of anode hole injection directly verified for oxides thicker than 55 A is able to model silicon dioxide breakdown accurately.

Inverted spacer transistor

Abstract: A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.

Method of making a three dimensional trench EEPROM cell structure

Abstract: The objects of the present invention are accomplished by merging a MOS-FET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate.

Method for forming a field-effect transistor including anodic oxidation of the gate

Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Process for high density split-gate memory cell for flash or EPROM

Abstract: A method and structure for manufacturing a high-density split gate memory cell, for a flash memory or EPROM, is described. Silicon islands are formed from a silicon substrate implanted with a first conductivity-imparting dopant. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over a portion of the vertical surfaces of the first dielectric layer, and acts as a floating gate for the high density split-gate memory cell. A source region is located in the silicon substrate, and is implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is located in the top of the silicon islands, and is also implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A second dielectric layer is formed over the top and side surfaces of the floating gate, and acts as an interpoly dielectric. A second conductive layer is formed over that remaining portion of the vertical surfaces of the first dielectric layer not covered by the first conductive layer, and surrounds the second dielectric layer, whereby the second conductive layer is a control gate.

Random telegraph signals in deep submicron n-MOSFET's

Abstract: Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO/sub 2/ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel. >

VDMOS transistor and manufacturing method therefor

Abstract: A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

Quasi-breakdown of ultrathin gate oxide under high field stress

Abstract: A new oxide failure mode of ultrathin gate oxide is reported. During high constant current stressing, V/sub G/ variation with time shows two distinct modes, i.e., a stable mode and a fluctuation mode named as quasi-breakdown. Once the quasi-breakdown starts, gate current in low field abruptly increases. From the experimental results, it could be concluded that the quasi-breakdown occurs when injected electrons travel in the oxide conduction band ballistically. Localized physical damage near the Si/SiO/sub 2/ interface is believed to be the cause of the quasi-breakdown, The great increase of gate current after the quasi-breakdown was modeled by a superposition of F-N tunneling current and direct tunneling current with a finite series resistance, and a good agreement has been found. >

Split-gate flash memory cell

Abstract: This patent discloses a split-gate flash memory cell having a vertical isolation gate and a process for making it. The inventive cell has better control and a denser memory array than conventional cells. By use of a vertical isolation gate a smaller cell size is obtained. The memory cell has a floating gate transistor formed in a substrate having a channel extending underneath a floating gate, and a vertical isolation transistor formed in the substrate having a channel parallel to a trench holding a portion of a polysilicon control gate and orthogonal to the channel of the floating gate transistor.

Method of providing a dielectric structure for semiconductor devices

Abstract: A dielectric structure on a substrate includes a primary dielectric layer on the substrate, the primary dielectric being a metal oxide, such as tantalum pentoxide, having a high dielectric constant, and a secondary dielectric layer, such as an oxide or nitride of silicon, on the primary dielectric layer. In one embodiment, a multi-layer structure includes a second primary dielectric layer disposed on the secondary dielectric layer, and a second secondary dielectric layer disposed on the second primary dielectric layer, each primary dielectric layer being in a first crystalline state characterized by low leakage current for a given applied electrical field. A method of forming a dielectric structure on a substrate includes forming a layer of a primary dielectric, which is a metal oxide having a high dielectric constant, forming a secondary dielectric layer on the primary dielectric layer, and annealing the primary dielectric layer.

Dynamic random access memory (DRAM) semiconductor device

Abstract: A semiconductor device comprising a semiconductor substrate of first conductivity type, a trench type element isolation region formed in a preset depth from the semiconductor substrate surface, an element region of the first conductivity type surrounded by the element isolation region, a gate trench for forming a gate electrode, the trench being formed in the semiconductor substrate with a smaller depth than the element isolation region and extending through the element region and element isolation region, a gate electrode buried in the bottom portion of the gate trench via a gate insulation film, and source and drain regions of a second conductivity type formed in the element region and separated from each other by the gate trench, wherein the top surface of the gate electrode lies higher than the bottom levels of the source and drain regions and lower than a contact surface of the source and drain regions.

Process for high density flash EPROM cell

Abstract: A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.

Ultra‐low‐temperature growth of high‐integrity gate oxide films by low‐energy ion‐assisted oxidation

Abstract: The gate oxide films have been grown at a temperature as low as 450 °C by direct oxidation of silicon. Such a low‐temperature oxidation has been realized by employing a precision controlled ion bombardment in an Ar/O2 mixed plasma for the surface activation. Perfectly controlled Ar ions give the bombardment energy for the oxide film growth. Dielectric breakdown fields of 10 MV/cm are achieved. Integration in a total low‐temperature device process has been demonstrated by fabricating self‐aligned Al‐gate metal‐oxide‐silicon field effect transistor (MOSFET) formed without any heat processing over 450 °C. The precise control of the ion bombardment is quite essential for the low‐temperature process.

Method for fabricating thin film transistor using anodic oxidation

Abstract: In a thin film transistor (TFT), a mask is formed on a gate electrode, and a porous anodic oxide is formed in both sides of the gate electrode using a relatively low voltage. A barrier anodic oxide is formed between the gate electrode and the porous anodic oxide and on the gate electrode using a relatively high voltage. A gate insulating film is etched using the barrier anodic oxide as a mask. The porous anodic oxide is selectively etched after etching barrier anodic oxide, to obtain a region of an active layer on which the gate insulating film is formed and the other region of the active layer on which the gate insulating film is not formed. An element including at least one of oxygen, nitrogen and carbon is introduced into the region of the active layer at high concentration in comparison with a concentration of the other region of the active layer. Further, N- or P-type impurity is introduced into the active layer. Accordingly, high resistance impurity regions are formed in both sides of a channel forming region.

Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/ testing

Abstract: The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power supply current I/sub DDQ/ is studied. The possible detection of this defect by current testing is explored in fully complementary CMOS circuits. The behavior of a transistor with its floating gate is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The poly-bulk and metal-poly capacitances are found to be two significant parameters in determining the degree of conduction on the affected transistor. The induced voltage in the floating gate and the quiescent current are estimated by analytical expressions. The model is compared with SPICE 2 simulations. Good agreement is observed between the simple analytical expressions, simulations and experimental measures performed on defective circuits. In addition, it is shown that the floating gate transistor can be modeled as a weakly conductive stuck-on transistor or as a stuck-open transistor depending on the values of the parameters characterizing the defect. >

Cross-point eeprom memory array

Abstract: A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24). Improved operating performance is obtained, in part, by fabricating the first silicon dioxide layer (12) of the ONO layer (17) to a greater thickness than the top silicon dioxide layer (16) of the ONO layer (17).

Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

Abstract: To optimize the V/sub th/ of double-gate SOI MOSFET's, we fabricated devices with p/sup +/ poly-Si for the front-gate electrode and n/sup +/ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V/sub th/ of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 /spl mu/m long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects. >

Formation of Metal/Ferroelectric/Insulator/Semiconductor Structure with a CeO2 Buffer Layer

Abstract: Experimental results derived from the capacitance vs voltage (C-V) characteristics of metal/ferroelectric/insulator/semiconductor (MFIS) structures are described. PbTiO3 ferroelectric films of 600 A thickness were grown on CeO2/Si(100) substrate by digital chemical vapor deposition (digital CVD). As the buffer layer between ferroelectric and Si substrate, 150-A-thick CeO2 intermediate epitaxial layers were grown on a (100) silicon substrate by vacuum evaporation. The density of surface states at the CeO2/Si(100) interface was estimated from the C-V characteristics of Al/ CeO2/Si(100) samples to be ~1011/cm2 eV. Epitaxial CeO2 films on Si(100) would therefore be expected to function as the gate oxide for MFS-FET's. Furthermore, the MFIS structure has ferroelectric switching properties, as demonstrated by the roughly 1-V threshold hysleresis in C-V characteristics. This structure is thus a first step toward high-performance MFIS-FET's.

Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs

Abstract: Ultra-high performance n-MOSFETs were fabricated with a tunneling gate oxide 1.5 nm thick. It was found that these devices operate well when the gate length is around 0.1 /spl mu/m, because gate leakage current falls in proportion to the gate length and the drain current increases in inverse proportion. A very high drivability of 1.1 mAspl mu/m at 15 V was obtained, even in devices with a 0.14 pm gate length. A record high transconductance, 1,010 mS/mm at room temperature was also obtained in 0.09 /spl mu/m MOSFETs. Confirmation was obtained that hot-carrier reliability improves as the gate oxide thickness is reduced, even in the 1.5 nm case. High current drive at the low supply voltage of 0.5 V was also demonstrated. We made clear that very high performance is obtained in Si MOSFETs, if we can use a high capacitance gate insulator. In future devices, the tunnel gate oxide may be a good candidate for such a gate film, depending upon their applications. >

Semiconductor device having vertical conduction transistors and cylindrical cell gates

Abstract: A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars. Each of the silicon pillars includes vertically stacked layers which serve as respective drain, channel, and source regions of a transistor.

Thin film semiconductor device with gate metal oxide and sidewall spacer

Abstract: A monolithic circuit comprises a plurality of thin film transistors. Source and drain regions of the TFT are provided with a metal silicide layer having a relatively low resistivity. Thereby, the effective distance between a gate and a source/drain electrode can be reduced.