Showing papers on "Low-dropout regulator published in 2020"

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

Abstract: A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns $di/dt$ ) with settling times < 20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail.

A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications

Abstract: Compact low dropout (LDO) with high current handling capability and superior transient response is gaining increasing attention for the battery-powered 5G mobile applications. In this article, a new multiple-loop design technique for fast-transient response LDO regulator design has been proposed and successfully implemented in a 0.13- $\mu \text{m}$ SOI CMOS process for portable smartphone and tablet PC applications. Its supply current capacity is more than 1 A, and its output voltage is from 1.2 to 1.8 V. The proposed LDO features a 10-mV undershoot and overshoot with 1-A/100-ns load current on a 1- $\mu \text{F}$ output capacitor. This superior transient performance is achieved by embodying a novel frequency compensation scheme without penalty of dc loop gain drop in large load current conditions. The dc loop gain is 60 dB and constant regardless of the fact that the load current varies from 0 to 1 A. This contributes to a small load regulation and line regulation of 0.6 $\mu \text{V}$ /A and 0.23 mV/V, respectively. The LDO consumes 35- $\mu \text{A}$ quiescent current in the mission mode and 5 $\mu \text{A}$ in the standby mode. The LDO silicon size is 325 $\mu \text{m}\,\,\times $ 106 $\mu \text{m}$ .

A Digital Low-Dropout Regulator With Autotuned PID Compensator and Dynamic Gain Control for Improved Transient Performance Under Process Variations and Aging

Abstract: This article demonstrates all-digital tuning and dynamic control of feedback compensator in digital low drop out regulators to enhance the transient performance under process and passive variations, aging, and load changes. The measured results from a 130-nm CMOS test-chip shows 2.1× improvement in transient performance under process variations and 30% improvement for aging-induced degradations. We demonstrate 55-ns setting time for a 5 to 45 mA load step in 100 ps, with 97.8% peak current efficiency.

Dual-summed flipped voltage follower LDO regulator with active feed-forward compensation

Abstract: In this paper, an internally compensated dual-summed flipped voltage follower (FVF) low drop-out (LDO) regulator is proposed This LDO uses a small miller capacitance (MC) and an active feed-forward compensation (AFFC) to internally stabilize the feedback loop The active feed-forward compensator shifts an RHP zero of the miller capacitance to the load-dependent LHP zero A simple RC high-pass filter enhances the overshoot transient response of the LDO and stabilizes the feedback loop further with increased phase margin This LDO achieves settling time of 110 ns during overshoot and 32 ns during undershoot with edge time of 25 ns

A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz

Abstract: High power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems-on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop-bandwidth. Typical LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system-level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1 $\mu \text {s}$ and has a quiescent current of 5.6 $\mu \text {A}$ . For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing.

Architectural Advancement of Digital Low-Dropout Regulators

Abstract: Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, event-driven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator

Abstract: A digitally assisted high-current low-dropout (LDO) regulator is proposed in this article. The LDO architecture combines two main types of regulators: digital LDOs and analog LDOs. The proposed architecture uses the digital loop for tracking large output current variations and the analog loop for steady-state operation. The dual loops have a loop controller for coherent operation. Hence, the proposed LDO inherits some advantages from both sides. It achieves high power supply rejection (PSR) from the analog part without ripples at the output. Compared with the analog loop, the digital loop has a faster settling time while consuming minimum static power. In this design, the maximum load is 245 mA. The PSR is −42 dB at 1 MHz for heavy loading conditions. The quiescent current ( ${I}{Q}$ ) is 300 $\mu \text{A}$ . When the 300-/100-ns (rising/falling) current step is applied at the load, the voltage peak is 71/37 mV, respectively. The proposed LDO achieves a competitive 7.4-ps figure of merit (FOM). The active area is approximately 0.056 mm2 in a TSMC40-nm process.

An efficient energy harvesting circuit for batteryless IoT devices

Abstract: A new energy harvesting circuit for battery-less IoT beacon tags is developed herein to maximize power conversion efficiency as well as high throughput power with a wide input–output range. This design energy harvest (EH) circuit incorporates a charge pump (CP) with shoot-through current suppression, a body selector circuit, a maximum power point tracking circuit (MPPT), a timing control circuit, a hysteresis control circuit and a low dropout regulator. Also in this MPPT circuit is a gated clock tuned in a self-adaptive fashion to match the input impedance of the EH circuit to the output impedance of the photovoltaic (PV) panel, thus achieving successfully maximum power point. The circuit is implemented in an integrated chip in an area of 1.2 mm2 via the TSMC 0.18 process. Experiments on the chip are conducted and the results show that the input voltage range is allowed from 0.55 to 1.7 V to effectively harvest the solar power from a flexible dye-sensitized solar cell. The achieved peak power conversion efficiency (PCE) is 77% at the input power of 52 μW. For a wide range of lighting luminance (300–1300 lx,) the achieved average PCE is more than 70%. The achieved wide input–output range and the maximum throughput power of 200 μW is much larger than others reported, while the 77% of PCE is close to that best power conversion efficiency reported.

A 0.5-V Capless LDO With 30-dB PSRR at 10-kHz Using a Lightweight Local Generated Supply

Abstract: An analog low dropout regulator (LDO) that can operate at ultra-low voltage (ULV) with high power supply rejection ratio (PSRR) is presented in this brief. The supplies of the error amplifier and the power stage in this LDO are separated, and a lightweight local generated supply (LLGS) is proposed to guarantee the proper function of the associated error amplifier in ULV mode. This LLGS assisted analog LDO has been experimentally verified in 0.13 $\mu \text{m}$ CMOS technology and it only occupies an active area of 0.035 mm2. Measurement results indicate that this LDO can achieve greater than 30 dB PSRR up to 10 kHz at supply voltage as low as 0.5 V.

A High-Efficiency and Fast-Transient Low-Dropout Regulator With Adaptive Pole Tracking Frequency Compensation Technique

Abstract: An advanced smooth pole tracking technique for a low dropout (LDO) regulator with a ceramic capacitor is presented in this article. Normally, the dominant pole is at the output of an LDO and becomes load dependent, which may cause a loop stability issue during the whole load-current application range. The proposed frequency compensation methodology with adaptive load resistor control of an error amplifier (EA) alleviates the problem and reduces the dependence of equivalent series resistance of an output capacitor. Moreover, combined with this compensation strategy, an ultrafast EA by utilizing a transconductance enhancement technique is proposed to greatly reduce output voltage spikes as well as response time of the LDO during transient. This circuit has been implemented in a 0.18-μm standard CMOS process and occupies an active chip area of 0.017 mm2. Experimental results show that it can deliver 150 mA load current at 200 mV dropout voltage. Good loop stability and transient responses are easily achieved without degrading other important LDO parameters.

A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability

Abstract: In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

A BGR-Recursive Low-Dropout Regulator Achieving High PSR in the Low- to Mid-Frequency Range

Abstract: This article proposes a bandgap reference (BGR) recursive low-dropout (LDO) regulator chip that achieves a high power supply rejection (PSR) in the low- to mid-frequency range. The presented LDO design enables the total PSR of LDO to be free from the finite ripple-rejection of the BGR circuit, resulting in low design complexity and low power consumption. To improve the PSR further, the gate buffer is modified to provide an additional ripple feedforward cancellation. The modified gate buffer also offers fast transient response and stable operation. Moreover, a light-load stabilizer loop is also suggested to provide high stability over all load conditions. A prototype chip able to supply up to 300 mA output current was implemented by 0.5- μ m 5-V CMOS devices. The PSR was measured to be –102 to –80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with C OUT ≥ 1 μ F. The proposed LDO consumes only 50 μ A at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit of 11 ps in the transient response.

An Output Capacitorless Low-Dropout Regulator With a Low-V DD Inverting Buffer for the Mobile Application

Abstract: To provide power to the latest mobile applications that use functions with heavy loads, in this letter, we present a capacitorless low-dropout regulator (LDO) that supplies a large load current up to 600 mA. The proposed buffer and the feedforward paths are used to provide a stable operation and fast response along with a large load current. Owing to these schemes, the proposed LDO has a high unity gain frequency of 2.85 MHz at 100 mA with a total compensation capacitance of 5.1 pF. In addition, the LDO operates under a wide input voltage range of 1.5–5.0 V owing to the low-VDD structure. Also, a power supply rejection ratio was –52 dB at 100 kHz. The chip was implemented with a small size of 0.082 mm2 using the I/O devices of a 0.18 μ m CMOS process with a minimum length of 0.5 μ m.

Design of an Adaptively Biased Low-Dropout Regulator With a Current Reusing Current-Mode OTA Using an Intuitive Analysis Method

Abstract: An adaptively biased low-dropout regulator (AB-LDO) with current mirror buffer has been proposed in previous literatures, which only solves a few of the specific problems of AB-LDO without additional synthetical analysis of the various performances. Based on the analysis, it is found that enhancing the current efficiency of operational transconductance amplifier (OTA) is a key factor to improve the performances of AB-LDO. A current reusing current-mode OTA (CRCM-OTA) with high current efficiency is proposed to apply to AB-LDO. Compared with the traditional AB-LDO, it can achieve an obvious improvement of AB-LDO performances including the current efficiency of AB-LDO, loop gain, and loop bandwidth without increasing the area and power consumption. This article also adopts an intuitive method different from the previous works to analyze the whole loop. The AB-LDO using an advanced CRCM-OTA was fabricated in SMIC 0.18 $\mu$ m CMOS process, which has a transient undershoot of 26.25 mV with an output capacitor of 1 $\mu$ F for a load step of 0–50 mA with edge time of 10 ns and realizes a performance figure of merit (FoM) value of 13.65 ps.

Fully Integrated Autonomous Interface With Maximum Power Point Tracking for Energy Harvesting TEGs With High Power Capacity

Abstract: In this article, a novel fully autonomous and integrated power management interface circuit is introduced for energy harvesting using thermoelectric generators (TEGs) to supply power to Internet of Thing nodes. The circuit consists of a self-starting dc-dc converter based on a dual-phase charge pump with LC-tank oscillator, a digital MPPT unit, and a 1-V LDO regulator. The novel maximum power point tracking (MPPT) algorithm avoids open-circuit state, and accommodates varying input power and ultra-low voltage conditions. Validation data from the fabricated test-chip in 180 nm standard CMOS technology indicates the circuit start-up voltage is as low as 170 mV. The maximum output power capacity is 0.5 mW, which is the highest noted in the literature for a fully integrated solution. The high output power at low cost is achieved with a peak system efficiency of 30%. The relatively low efficiency is expected, since the focus of the design is high power capacity at low cost. The MPPT algorithm reaches 98% maximum accuracy for a source output resistance of 40 Ω, which is typical for wearable TEG modules.

A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR Technique in 0.18- $\mu$ m CMOS Process

Abstract: In this article, a dual loop-compensated, fast-transient, low-dropout regulator (LDO) is proposed for battery-powered applications. It is successfully implemented in a 0.18- $\mu \text{m}$ CMOS process with a total silicon area of $210\,\,\mu \text{m}\,\,\times 593\,\,\mu \text{m}$ . The proposed LDO is composed of two feedback loops. The fast feedback loop (FFL) employs direct output voltage spike detection through capacitive coupling, resulting in significantly improved, large signal transient response and loop bandwidth at the same time. Its voltage spike is 15 mV for a load step of 600 mA. The proposed LDO has a loop bandwidth of 2.3 MHz at a load current of 600 mA with a 30- $\mu \text{A}$ no-load bias current. A power transistor with pseudo-equivalent series resistance (ESR) technique is proposed for loop stability improvement. It enables the usage of the low-cost, multilayer ceramic capacitors in mobile applications. The constant biased voltage feedback loop (VFL) has a loop gain larger than 60 dB under all load conditions, which enables a good line and load regulation.

A Fast-Transient Response Digital Low-Dropout Regulator With Dual-Modes Tuning Technique

Abstract: A fast transient response digital low dropout (LDO) regulator with a low quiescent current is proposed for power management applications in a self-powered wireless sensor system. The digital LDO incorporates both bisection method (BM) and steady-state tuning techniques to enhance the current efficiency and transient response speed. In steady-state period, the digital LDO works at steady-state mode and only one PMOS is switched at each clock edge for high accuracy and current efficiency. Once the variation of output voltage exceeds the detection boundaries, the BM mode is triggered and the required array conductance can be found in a short response time. The proposed digital LDO is fabricated using 65nm CMOS process. The measurement results show that with the load current switching between 0.1 mA and 4.5 mA, the proposed digital LDO shows a transient response time of 5.9 $\mu \text{s}$ with a maximum undershoot voltage of 118 mV at a regulated output voltage of 0.55V. The current efficiency is 99.7% and the figure of merit is 62.2 ps.

A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches

Abstract: Low-power system-on-a-chip (SoC) with multiple voltage domains often adopts voltage scaling approaches to optimize power usage while maintaining enough performance. Voltage regulators having flexible output configurability, fast transient response, and high-power noise rejection ability are indispensable for this application scenario. A low-dropout (LDO) regulator was proposed in this article to convert an input of 1.9–1.1 V to an output of 1.1–0.2 V with a 10-mV tuning resolution by raising the concept of programmable recursively divide-by-two resistor array (PRDTRA). A high gain-bandwidth main regulation loop of the proposed LDO regulator was accompanied by a transient acceleration (TA) path and a unity power noise gain generator to achieve a 28-mV output variation during 0–100-mA load transient test while keeping a 60-dB power supply rejection ratio (PSRR) over a frequency band of 0–1 MHz. Performance evaluations show the performance superiority of the proposed LDO regulator.

A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC–DC Switching Converters

Abstract: The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μ A and reduces the switching power loss through variable switching frequency control. With a load step of 1–20 mA, the transient response time is 1.3 μ s and the peak current efficiency is 99.8% at heavy loads.

A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications

Abstract: In this paper, a high performance adaptive digital low-dropout voltage regulator (ADLDO) is proposed for Internet-of-Things (IoT) applications. In the proposed ADLDO, a fully synthesizable adaptive digital controller is designed. It automatically senses load variations and adaptively controls multi-loop architecture to reduce quiescent current, minimize output voltage ripples and achieve fast transient response. The multi-loop architecture with hill climbing reduces the total bi-directional shift registers length which results in the reduced leakage current in the transistor-switch-array (TSA), and improves the recovery time and output DC voltage accuracy. A dithering technique is introduced to eliminate the limit cycle oscillation (LCO) and improve the performance of the regulator. The dynamic frequency scaling (DFS) mechanism is proposed for reducing controller power consumption in steady state. In order to reduce the offset and output voltage error, a dynamic latch comparator is utilized. When the input supply voltage is varied from 0.5 V to 1 V, the measured output voltage ranges from 0.45 V to 0.95 V with 50 mV dropout voltage. The operating frequency is 10 MHz with fast transient response and quiescent current of 350 ns and 3.7μA, respectively. The maximum measured power and current efficiencies are 89.7 % and 99.97 %, respectively, with 1.9 mV output voltage ripples. Measured load and line regulations are 2.2 mV/mA and 9.5 mV/V respectively. The proposed circuit is implemented in 28 nm CMOS process and occupies 0.016 mm 2 chip area.

High-PSR and fast-transient LDO regulator with nested adaptive FVF structure

Abstract: This paper presents a low-dropout (LDO) regulator using nested adaptive flipped voltage follower (FVF) to achieve fast-transient response and improve both power supply rejection ratio (PSR) and line regulation It features a maximum ripple of 46mV at output when the load current steps between $1 \mu \mathrm{A}$ and 20mA in 10ps, with the advantages of simulated PSR of -5852dB at 1MHz and -4166dB at 10MHz

A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme

Abstract: This brief presents a highly synthesizable digital low-dropout regulator (DLDO) based on adaptive clocking and an incremental regulation scheme. With these features, the clock frequency of the shift registers is adaptively changed according to load voltage, and most of the voltage droop is stably recovered in one clock transition using voltage-unit-resolution pass gates. Moreover, the DLDO is fully synthesized using an auto place-and-route (P&R) process except pass gates and an on-chip metal-oxide-metal (MOM) output capacitor. Therefore, the synthesizable DLDO offers a scalable and portable architecture that has low design cost. The proposed DLDO is fabricated in the 28-nm CMOS technology with an active area of 0.0056 mm2. The ranges of input and output voltages are from 0.5 V to 1.0 V and from 0.45 V to 0.95 V, respectively. During recovery from a 2-mA load-current step with a 5-ns slew, the DLDO achieves 92-mV voltage droop and 83-ns settling time. The quiescent current is $7.87~\mu \text{A}$ , and the maximum load current and peak current efficiency are 4 mA and 99.8 %, respectively, with a 0.5-V supply.

A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO With 8-Cycles Mean Settling Time and 9-Bit Regulating Resolution in 180-nm CMOS

Abstract: This brief presents an all-digital low dropout regulator (DLDO) with high regulating resolution and fast transient tracking by combining novel interval-searching algorithm and recover acceleration techniques. By bringing forth an enhanced interval-searching algorithm (ISA) with 9-bit register regulating precision, the output can be stabilized within 8 cycles when the load changes. A recover acceleration (RA) technique is proposed to improve the transient response and stability. The DLDO is fabricated with standard 180-nm CMOS process. The proposed DLDO needs 390 pF output capacitance and can provide as much as 170 mA load current. The measured load regulation is 0.11 mV/mA at 0.9 V output with 160 mA load current range. The maximum current efficiency is up to 99.71%. The two FOMs of 2.03 ps and 0.362 pF are also achieved to illustrate the merits of this design.

An Output-Capacitorless Low-Dropout Regulator with High Slew Rate and Unity-Gain Bandwidth

Abstract: This paper presents a fast-response output-capacitorless low-dropout regulator (OCL-LDO) using a high slew-rate input stage and improved multipath nested Miller compensation (MNMC). With the specially-designed input stage, the quality factor (Q) of the transfer loop is greatly reduced. The circuit is implemented in a standard 65-nm CMOS process. The total on-chip compensation capacitance is 0.5 pF only. The designed OCL-LDO regulator features over 150 MHz unity-gain bandwidth (UGB) at zero load and keeps UGB higher than 100 MHz up to 45 mA loading. For the maximum 60-mA load transient with 10-ns edge time, the voltage spikes are controlled around 20 mV.

32.4 A 0.4-to-1.2V 0.0057mm 2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement

Abstract: Digital low-dropout regulators (DLDOs) are commonly used in low-power system-on-chips (SoCs) because of their low-voltage operation and fast transient response via the digital control of a power gate. However, the digital control of the power gate results in an output voltage ripple and a decrease in the power-supply rejection (PSR). In addition, the transient performance of DLDOs depends strongly on the operating clock frequency. Several techniques such as event-driven operation [1], VCO-embedded time-based control [2], and computed regulation [3] have been proposed to reduce the dependency on the operating clock frequency. Nonetheless, the output voltage ripple and PSR degradation of DLDOs still need to be addressed. Although an inverter-based analog LDO [4] that provides a low-voltage operation and a wide-band PSR has been proposed, as compared to DLDOs it has a slow transient response and narrow input voltage range.

A 0.58-to-0.9-V Input 0.53-V Output 2.4- $\mu$ W Current-Feedback Low-Dropout Regulator With 99.8% Current Efficiency

Abstract: This letter presents an output capacitor-less low-dropout regulator (LDO) topology that can operate from 0.58-to-0.9-V supply, and has a minimum dropout voltage of 50 mV. Compared with traditional analog LDOs, the proposed design incorporates a current reference into the regulator loop and uses current feedback to alleviate the design constraints caused by the limited voltage headroom. The LDO is implemented in a 0.13- $\mu \text{m}$ standard-threshold-voltage CMOS process. Measurement results show that depending on the supply voltage the quiescent power consumption is from 2.4 to 3.6 $\mu \text{W}$ , and the current efficiency is 99.8%. The mean value of the output voltage of 16 samples is 0.53 V and the standard deviation is around 4 mV. The load current range of the proposed LDO is from 0 to 3 mA, and it is capable of driving a load capacitor of up to 120 pF.

A Fully Integrated 1.2V LDO Regulator

Abstract: This work presents a fully integrated low-drop out voltage regulator that achieves a fast-transient response by utilizing two feedback mechanisms The first feedback mechanism is an analog regulation that includes an error amplifier The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS based or a PMOS based current DAC The DAC provides current in opposite polarity to the sharp transient change in load current As a result, sharp changes in load current is addressed by high-speed current DACs and is not limited by the performance of the error amplifier The LDO was implemented using 180nm CMOS technology devices It uses a supply voltage input range of 16 V – 20 V and produces an output voltage of 12 V In simulations, the LDO regulator achieves 188 uA quiescent current, -56 dB PSRR @ 1 KHz noise frequency and an output voltage drop of around 200 mV for a load current step of 100 mA

Stability analysis and experimental validation of the supercapacitor-assisted low-dropout regulator

Abstract: The supercapacitor-assisted low-dropout (SCALDO) regulator is a unique new design approach to develop high efficiency, high current and low noise DC–DC converters, where a supercapacitor (SC) is used in the series path of a low dropout (LDO) regulator to act as a lossless voltage dropper. In the published literature, there has been much discussion about the stability of an LDO regulator, where different approaches are applied to frequency compensate depending on the LDO architecture. Given the case that the SCALDO technique is a combination of an LDO regulator and an SC, this study presents an analysis and experimental validation of the stability, based on a 12–5 V SCALDO prototype, proving that the effect of the SC energy recovery method does not make the overall regulator carry a stability issue in general.

Design of CMOS low-dropout voltage regulator for power management integrated circuit in 0.18-µm technology

Abstract: A low-dropout (LDO) voltage regulator is the main component used in the majority of portable electronic application since it is used as power management unit in those applications. In this paper, a LDO regulator for the power management integrated circuit in 0.18-µm CMOS technology using Cadence software is presented. The error amplifier of the proposed LDO employed seven transistors for current mirror. Meanwhile, the PMOS transistor is used as a pass element transistor to control the voltage variation. The resistors are used as a feedback network circuit while the capacitor is used to minimise the variation of output voltage. The simulation results show that the proposed design provides a 2.41 V constant output voltage for the supply voltage ranges of 2.55 V to 3.55 V. The dropout voltage of 140 mV is achieved with 1.48 mW power consumption. The line regulation is 1.0 mV/V and the load regulation is 0.41 mV/A, while the layout of the proposed regulator is 27 µm x 34 µm.

A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit

Abstract: In this brief, a low quiescent output-capacitor-less NMOS low-dropout regulator using a coarse-fine charge-pump circuit is proposed. The proposed charge-pump low-dropout regulator (CP-LDO) achieves the output-capacitor-less LDO using a NMOS power transistor, a comparator, and a coarse-fine charge-pump circuit. It reduces both the quiescent current and the capacitor size of the charge-pump by directly adjusting the gate voltage of the NMOS power transistor. It improves both the transient response and the quiescent power efficiency by coarsely and finely adjusting the gate voltage, respectively. This also can remove the output glitch voltage. The proposed CP-LDO was fabricated using a 65nm CMOS process. Its area is 0.01 mm2. The maximum undershoot voltage is 108 mV when the load current changes from 0.5 mA to 10.5mA within the edge time of 1ns. The total capacitor of the CP-LDO is 7.6 pF. The quiescent current is 162 nA at VIN = 0.5 V and ${f} _{\mathrm{ CLK}}=1$ MHz. The figure of merit is 0.0013 ps.