Showing papers on "Memory refresh published in 2015"

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Abstract: In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging memory technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), and hybrid non-volatile plus DRAM memory systems. Compared to existing memory simulators, NVMain 2.0 features a flexible user interface with compelling simulation speed and the capability of providing sub-array-level parallelism, fine-grained refresh, MLC and data encoder modeling, and distributed energy profiling.

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

Abstract: Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as nonvolatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this paper, we provide a very detailed analysis of SOT-MRAM at both the circuit- and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that a hybrid -combination of SRAM for the L1-Data-cache, SOT-MRAM for the L1-Instruction-cache and L2-cache can reduce the energy consumption by 60% while the performance increases by 1% compared to an SRAM-only configuration. Moreover, the retention failure probability of SOT-MRAM is $27\boldsymbol {\times }$ smaller than the probability of radiation-induced Soft Errors in SRAM, for a 65nm technology node. All of these advantages together make SOT-MRAM a viable choice for microprocessor caches.

Phase-Change and Redox-Based Resistive Switching Memories

Abstract: This paper addresses the two main resistive switching (RS) memory technologies: phase-change memory (PCM) and redox-based resistive random access memory (ReRAM). It will review the basic concepts, the initial promises, and current state of the art, with focus on possible scaling pathways for low-power operation and dense, true 3-D memory. Recent physical insights and new potential concepts will be discussed.

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

Abstract: Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Abstract: Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1] Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2] Advanced perpendicular STT-MRAM achieve ∼3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3] Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power

Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions

Abstract: DRAM cells require periodic refreshing to preserve data. In JEDEC DDRx devices, a refresh operation is performed via an auto-refresh command, which refreshes multiple rows in multiple banks simultaneously. The internal implementation of auto-refresh is completely opaque outside the DRAM --- all the memory controller can do is to instruct the DRAM to refresh itself --- the DRAM handles all else, in particular determining which rows in which banks are to be refreshed. This is in conflict with a large body of research on reducing the refresh overhead, in which the memory controller needs fine-grained control over which regions of the memory are refreshed. For example, prior works exploit the fact that a subset of DRAM rows can be refreshed at a slower rate than other rows due to access rate or retention period variations. However, such row-granularity approaches cannot use the standard auto-refresh command, which refreshes an entire batch of rows at once and does not permit skipping of rows. Consequently, prior schemes are forced to use explicit sequences of activate (ACT) and precharge (PRE) operations to mimic row-level refreshing. The drawback is that, compared to using JEDEC's auto-refresh mechanism, using explicit ACT and PRE commands is inefficient, both in terms of performance and power. In this paper, we show that even when skipping a high percentage of refresh operations, existing row-granurality refresh techniques are mostly ineffective due to the inherent efficiency disparity between ACT/PRE and the JEDEC auto-refresh mechanism. We propose a modification to the DRAM that extends its existing control-register access protocol to include the DRAM's internal refresh counter. We also introduce a new "dummy refresh" command that skips refresh operations and simply increments the internal counter. We show that these modifications allow a memory controller to reduce as many refreshes as in prior work, while achieving significant energy and performance advantages by using auto-refresh most of the time.

Comparison operations in memory

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Method and apparatus for calibrating write timing in a memory system

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period

Maintenance operations in a DRAM

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Resistive memory architectures with multiple memory cells per access device

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Method, system and device for complementary non-volatile memory device operation

Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device.

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Abstract: Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energy-efficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memristive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.

Method, system and device for non-volatile memory device operation

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Read disturb and data retention handling for nand devices

Abstract: Systems, methods, and apparatus are herein disclosed for reducing read disturb and data retention errors in FLASH memory devices designed for long lifespans, such as greater than 10 or 15 years. Read disturb errors can be reduced by maintaining a read counter stored in a volatile memory and a FASTMAP memory block of the FLASH memory. When the read counter meets a threshold, then the associated memory block can be scheduled for scrubbing. Data retentions errors can be reduced by maintaining a last-erase timestamp in metadata of each memory block of a FLASH memory. When the last-erase timestamp associated with a given memory block meets a threshold, then the memory block can be scheduled for scrubbing.

In-Memory Data Rearrangement for Irregular, Data-Intensive Computing

Abstract: The data rearrangement engine (DRE) performs in-memory data restructuring to accelerate irregular, data-intensive applications. An emulation on a field-programmable gate array shows how the DRE could improve speedup, memory bandwidth, and energy consumption on three representative benchmarks.

Efficient Memory-Addressing Algorithms for FFT Processor Design

Abstract: This paper explores efficient memory management schemes for memory-based architectures of the fast Fourier transform (FFT). A data relocation scheme that merges multiple banks to lower the area requirement and power dissipation of memory-based FFT architectures is proposed. The proposed memory-addressing method can effectively deal with single-port, merged-bank memory with high-radix processing elements. Compared with conventional memory-based FFT designs using dual-port memory, the derived architecture has better performance in terms of area and power consumption. The proposed scheme is extended to a cached-memory FFT architecture to further reduce power dissipation. An 8192-point cached-memory FFT processor is implemented for digital video broadcasting-terrestrial/handheld applications by using 0.18- $\mu $ m 1P6M CMOS technology. Experimental results show that the proposed memory scheme consumes 10.1%–29.3% less area and 9.6%–67.9% less power compared with those of the multibank design.

A Novel Non-Destructive Read/Write Circuit for Memristor-Based Memory Arrays

Abstract: Emerging nonvolatile universal memory technology is vital for providing the huge storage capabilities, which is needed for nanocomputing facilities. Memristor, which is recently discovered and known as the missing fourth circuit element, is a potential candidate for the next-generation memory. Memristor has received extra attention in the last few years. To support this effort, this paper presents a novel read/write circuit that facilitates the reading and writing operation of the Memristor device as a memory element. The advantages of the proposed read/write circuit are threefold. First, the proposed circuit has a nondestructive successive reading cycle capability. Second, it occupies less die area. Finally, the proposed read/write circuit offers a significant improvement in power consumption and delay time compared with other read/write circuits.

Semiconductor memory devices, memory systems including the same and methods of operating the same

Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Cryptographic protection of information in a processing system

Abstract: A processor [102] employs a hardware encryption module [115] in the processor's memory access path to cryptographic ally isolate secure information. In some embodiments, the encryption module is located at a memory controller [110] (e.g. northbridge) of the processor, and each memory access provided to the memory controller indicates whether the access is a secure memory access, indicating the data associated with the memory access is designated for cryptographic protection, or a non-secure memory access. For secure memory accesses, the encryption module performs encryption (for write accesses) or decryption (for read accesses) of the data associated with the memory access.

Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator

Abstract: Memory-based physical unclonable functions (PUFs) have been studied and developed as powerful primitives to generate device-specific random keys, which can be used for various security applications. However, the existing memory-based PUFs need to safely buffer the data bits in the memory before it is used to produce random bits, resulting in additional area/energy consumption and potential data security issues. In this paper, we propose a new memory-based PUF that exploits the nonvolatility and random variability of emerging memory technologies to produce random bits. Unlike conventional implementations, the random bit generation process of our proposed PUF does not disturb the data bits already stored in the memory. To satisfy the quality requirements for both memory and PUF applications, we also propose a general method to find the optimal design point of emerging nonvolatile memory (eNVM)-based PUF. An illustrative design using spin-transfer torque magnetic RAM exhibits desirable results using our method. Compared to the conventional types of memory-based PUFs, eNVM-based PUFs features enhanced security as cryptographic primitives and lower area and energy cost as data storage.

Endurance-Aware Allocation of Data Variables on NVM-Based Scratchpad Memory in Real-Time Embedded Systems

Abstract: Nonvolatile memory (NVM) has many benefits compared to the traditional static RAM, such as improved reliability and reduced power consumption, but it has long write latency and limited write endurance. Scratchpad memory (SPM) is software-managed small on-chip memory for improving system performance and predicability. We consider SPM based on spin-transfer torque RAM, a type of NVM with high performance and good endurance. We present algorithms for allocating data variables to SPM and distribute write activity evenly in the SPM address space, in order to achieve wear-leveling and prolong the lifetime of NVM. We present two optimization algorithms for minimizing system CPU utilization subject to NVM lifetime constraints: 1) an optimal algorithm based on ILP and 2) an efficient heuristic algorithm that can obtain close-to-optimal solutions.

Device and method for repairing memory cell and memory system including the device

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Flash memory device using adaptive program verification scheme and related method of operation

Abstract: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.

High performance AXI-4.0 based interconnect for extensible smart memory cubes

Abstract: The recent technological breakthrough represented by the Hybrid Memory Cube is on its way to improve bandwidth, power consumption, and density. This is while heterogeneous 3D integration has provided another opportunity for revisiting near memory computation to fill the gap between the processors and memories even further. In this paper, we take the first step towards a "Smart Memory Cube (SMC)", a fully backward compatible and modular extension to the standard HMC, supporting near memory computation on its Logic Base (LoB), through a high performance interconnect designed for this purpose. The main feature of SMC is the high bandwidth, low latency, and AXI-4.0 compatible interconnect, designed to serve the huge bandwidth demand by HMC's serial links, and to provide extra bandwidth to a processor-in-memory (PIM) embedded in the Logic Base (LoB). Our results obtained from cycle accurate simulation demonstrate that this interconnect can easily meet the demands of current and future projections of HMC (Up to 87GB/s READ bandwidth with 4 serial links and 16 memory vaults, and 175GB/s with 8 serial links and 32 memory vaults, for injected random traffic). Moreover, the interference between the PIM traffic and the main links was found to be negligible with execution time increase of less than 5%, and average memory access time increase of less than 15% when 56GB/s bandwidth is requested by the main links and 15GB/s bandwidth is delivered to the PIM port. Moreover, preliminary logic synthesis with Synopsys Design Compiler confirms that our interconnect is implementable and realistic.

Out of order memory command fetching

Abstract: A system and method that allows out of order fetching of host non-volatile memory commands can improve and maximize the memory device performance. The memory device can examine the non-volatile memory command headers available in the non-volatile memory command queue to select one or more, non-volatile memory commands to be fetched, in an optimum order and executed according to currently available resources in the memory device. The memory device can optimize performance of the non-volatile memory commands by re-ordering the host commands fetched from the host memory.

Josephson magnetic random access memory with an inductive-shunt

Abstract: A memory system includes a word-line coupled to memory cells in a row, and a bit-line coupled to memory cells in a column. Each of the memory cells includes a memory storage element including a Josephson junction configured to be in either a first state or a second state in response to an application of a word-line current to the Josephson junction. A read operation is performed on the at least one memory storage element by an application of a bit-line current to the bit-line. At least one inductive-shunt, coupled in parallel to the at least one memory storage element, is configured to, after the read operation, remove at least a substantial portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the bit-line during the read operation.

CAUSE: Critical Application Usage-Aware Memory System using Non-volatile Memory for Mobile Devices

Abstract: Mobile devices are severely limited in memory, which affects critical user-experience metrics such as application service time. Emerging non-volatile memory (NVM) technologies such as STT-RAM and PCM are ideal candidates to provide higher memory capacity with negligible energy overhead. However, existing memory management systems overlook mobile users application usage which provides crucial cues for improving user experience. In this paper, we propose CAUSE, a novel memory system based on DRAM-NVM hybrid memory architecture. CAUSE takes explicit account of the application usage patterns to distinguish data criticality and identify suitable swap candidates. We also devise NVM hardware design optimized for the access characteristics of the swapped pages. We evaluate CAUSE on a real Android smartphone and NVSim simulator using user application usage logs. Our experimental results show that the proposed technique achieves 32% faster launch time for mobile applications while reducing energy cost by 90% and 44% on average over non-optimized STT-RAM and PCM, respectively.

Memory system, program method thereof, and computing system including the same

Abstract: Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device.