Showing papers on "Microelectronics published in 2008"

A Thin Film Approach to Engineering Functionality into Oxides

Abstract: The broad spectrum of electronic and optical properties exhibited by oxides offers tremendous opportunities for microelectronic devices, especially when a combination of properties in a single device is desired Here we describe the use of reactive molecular-beam epitaxy and pulsed-laser deposition to synthesize functional oxides, including ferroelectrics, ferromagnets, and materials that are both at the same time Owing to the dependence of properties on direction, it is often optimal to grow functional oxides in particular directions to maximize their properties for a specific application But these thin film techniques offer more than orientation control; customization of the film structure down to the atomic-layer level is possible Numerous examples of the controlled epitaxial growth of oxides with perovskite and perovskite-related structures, including superlattices and metastable phases, are shown In addition to integrating functional oxides with conventional semiconductors, standard semiconductor practices involving epitaxial strain, confined thickness, and modulation doping can also be applied to oxide thin films Results of fundamental scientific importance as well as results revealing the tremendous potential of utilizing functional oxide thin films to create devices with enhanced performance are described

Epitaxial Graphene Transistors on SiC Substrates

Abstract: This paper describes the behavior of top-gated transistors fabricated using carbon, specifically epitaxial graphene on SiC, as the active material. Although graphene devices have been built before, in this paper, we provide the first demonstration and systematic evaluation of arrays of a large number of transistors produced using standard microelectronics methods. The graphene devices presented feature high-k dielectric, mobilities up to 5000 cm2/Vldr s, and Ion/Ioff ratios of up to seven, and are methodically analyzed to provide insight into the substrate properties. Typical of graphene, these micrometer-scale devices have negligible band gaps and, therefore, large leakage currents.

Epitaxial graphene transistors on SiC substrates

Abstract: This paper describes the behavior of top gated transistors fabricated using carbon, particularly epitaxial graphene on SiC, as the active material. In the past decade research has identified carbon-based electronics as a possible alternative to silicon-based electronics. This enthusiasm was spurred by high carbon nanotube carrier mobilities. However, nanotube production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic carbon, can overcome some of these problems and therefore is a promising new electronic material. Although graphene devices have been built before, in this work we provide the first demonstration and systematic evaluation of arrays of a large number of transistors entirely produced using standard microelectronics methods. Graphene devices presented feature high-k dielectric, mobilities up to 5000 cm2/Vs and, Ion/Ioff ratios of up to 7, and are methodically analyzed to provide insight into the substrate properties. Typical of graphene, these micron-scale devices have negligible band gaps and therefore large leakage currents.

Technologies for Cofabricating MEMS and Electronics

Abstract: Microfabrication technologies initially developed for integrated electronics have been successfully applied to batch-fabricate a wide variety of micromechanical structures for sensing, actuating, or signal-processing functions such as filters. By appropriately combining the deposition, etching, and lithography steps for microelectromechanical devices with those needed for microelectronic devices, it is possible to fabricate an integrated microsystem in a single process sequence. This paper reviews the strategies for cofabrication, with an emphasis on modular approaches that do not mix the two process sequences. The integrated processes are discussed using examples of physical sensors (infrared imagers and inertial sensors), chemical and biochemical sensors, electrostatic and thermal actuators for displays and optical switching, and nonvolatile memories. By adding new functionality to integrated electronics, the use of microelectromechanical systems is opening new applications in sensing and actuating, as well as enhancing the performance of analog and digital integrated circuits.

Self-transducing silicon nanowire electromechanical systems at room temperature.

Abstract: Electronic readout of the motions of genuinely nanoscale mechanical devices at room temperature imposes an important challenge for the integration and application of nanoelectromechanical systems (NEMS). Here, we report the first experiments on piezoresistively transduced very high frequency Si nanowire (SiNW) resonators with on-chip electronic actuation at room temperature. We have demonstrated that, for very thin (∼90 nm down to ∼30 nm) SiNWs, their time-varying strain can be exploited for self-transducing the devices’ resonant motions at frequencies as high as ∼100 MHz. The strain of wire elongation, which is only second-order in doubly clamped structures, enables efficient displacement transducer because of the enhanced piezoresistance effect in these SiNWs. This intrinsically integrated transducer is uniquely suited for a class of very thin wires and beams where metallization and multilayer complex patterning on devices become impractical. The 30 nm thin SiNW NEMS offer exceptional mass sensitivities in the subzeptogram range. This demonstration makes it promising to advance toward NEMS sensors based on ultrathin and even molecular-scale SiNWs, and their monolithic integration with microelectronics on the same chip.

Carbon nanotube thermal interface material for high-brightness light-emitting-diode cooling

Abstract: Aligned carbon nanotube (CNT) arrays were fabricated from a multilayer catalyst configuration by microwave plasma-enhanced chemical vapor deposition (PECVD). The effects of the thickness and annealing of the aluminum layer on the CNT synthesis and thermal performance were investigated. An experimental study of thermal resistance across the CNT array interface using the modified ASTM D5470 standard was conducted. It was demonstrated that the CNT-thermal interface material (CNT-TIM) reduced the thermal interfacial resistance significantly compared with the state-of-art commercial TIM. The optimized thermal resistance of the CNT arrays is as low as 7 mm2 K W−1. The light performance of high-brightness light-emitting diode (HB-LED) packages using the aligned CNT-TIM was tested. The results indicated that the light output power was greatly improved with the use of the CNT-TIM. The usage of the CNT-TIM can be also extended to other microelectronics thermal management applications.

Formation and characterization of organic monolayers on semiconductor surfaces.

Abstract: Organic-semiconductor interfaces are playing increasingly important roles in fields ranging from electronics to nanotechnology to biosensing. The continuing decrease in microelectronic device feature sizes is raising an especially great interest in understanding how to integrate molecular systems with conventional, inorganic microelectronic materials, particularly silicon. The explosion of interest in the biological sciences has provided further impetus for learning how to integrate biological molecules and systems with microelectronics to form true bioelectronic systems. Organic monolayers present an excellent opportunity for surmounting many of the practical barriers that have hindered the full integration of microelectronics technology with organic and biological systems. Of all the semiconductor materials, silicon and diamond stand out as unique. This review focuses upon the preparation and characterization of organic and biomolecular layers on semiconductor surfaces, with special emphasis on monolaye...

The Intramolecular Junctions of Carbon Nanotubes

Abstract: For the miniaturization of microelectronics, carbon nanotubes (CNTs) are regarded as ideal candidates for the next generation of nanoelectronics because of their excellent properties. To realize CNT-based electronics, intramolecular junctions are required components, which can not only connect different CNTs for integration, but can also act as functional building blocks in the circuit, such as rectifiers, field-effect transistors, switches, amplifiers, photoelectrical devices, etc. Therefore, intense attention has been focused on this topic and many advances have been achieved, especially in recent years. On the other hand, some challenges also exist. To provide researchers with a comprehensive overview of this field, this review discusses the synthesis, properties, and applications of intramolecular junctions of CNTs in detail. Among them, the applications of CNT integration are discussed specially. Furthermore, a brief summary and an outlook of future work are provided.

Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices

Abstract: Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die.

Microelectronic devices and methods for forming interconnects in microelectronic devices

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

High-performance organic integrated circuits based on solution processable polymer-small molecule blends

Abstract: The prospect of realizing high-performance organic circuits via large-area fabrication is attractive for many applications of organic microelectronics. Here we report solution processed organic field-effect transistors and circuits based on polymer-small molecule blends comprising of polytriarylamine and 5,11-bis(triethylsilylethynyl) anthradithiophene. By optimizing blend composition and deposition conditions we are able to demonstrate short channel, bottom-gate, bottom-contact transistors with high mobility and excellent reproducibility. Using these transistors we have built unipolar voltage inverters and ring oscillators with a single stage delay of 712 ns. These are among the fastest organic circuits reported to date and could satisfy the performance requirements of low-end electronic applications.

Reconstituted wafer level stacking

Abstract: A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches. Individual stacked microelectronic units may be separated from the stacked microelectronic assembly by any suitable dicing, sawing or breaking technique.

Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers

Abstract: Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stand-off having a compartment configured to contain the image sensor. The stand-off has a coefficient of thermal expansion at least substantially the same as that of the first substrate. The optical device can further include an optics element in alignment with the compartment of the stand-off. The stand-off can be formed by etching a compartment into a silicon wafer or a wafer of another material having a coefficient of thermal expansion at least substantially the same as that of the substrate upon which the image sensor is formed. The optics elements can be formed integrally with the stand-offs or separately attached to a cover supported by the stand-offs.

Power-Conditioning Circuitry for a Self-Powered System Based on Micro PZT Generators in a 0.13- $\mu\hbox{m}$ Low-Voltage Low-Power Technology

Abstract: The concept and design of a power-conditioning circuit for an autonomous low-power system-in-package (SiP) is presented in this paper. The SiP's main power source is based on the use of micropiezoelectric generators. The electrical model of the power source, which has been obtained based on experimental measurements and implemented on Cadence Analog Artist's Spectre simulation environment, is explained. The model has been used to simulate the power source with the power-conditioning electronics over the entire design process. Finally, the simulated and experimental results of the developed integrated power circuits, which are formed by a rectifier and a low-power bandgap reference voltage source to define the threshold voltage for the closed-loop regulation process, are also shown. These circuits have been designed using a commercial 0.13-mum technology from ST Microelectronics through the multi-projects circuits (CMP) techniques of informatics and microelectronics for integrated systems architecture (TIMA) service.

Development of Silicon Photonics Devices Using Microelectronic Tools for the Integration on Top of a CMOS Wafer

Abstract: Photonics on CMOS is the integration of microelectronics technology and optics components to enable either improved functionality of the electronic circuit or miniaturization of optical functions. The integration of a photonic layer on an electronic circuit has been studied with three routes. For combined fabrication at the front end level, several building blocks using a silicon on insulator rib technology have been developed: slightly etched rib waveguide with low (0.1 dB/cm) propagation loss, a high speed and high responsivity Ge integrated photodetector and a 10 GHz Si modulators. Next, a wafer bonding of silicon rib and stripe technologies was achieved above the metallization layers of a CMOS wafer. Last, direct fabrication of a photonic layer at the back-end level was achieved using low-temperature processes with amorphous silicon waveguide (loss 5 dB/cm), followed by the molecular bonding of InP dice and by the processing in microelectronics environment of InP sources and detector.

Size effects in small scaled lead-free solder joints

Abstract: Due to the ongoing miniaturization in modern microelectronics reliability and quality control of microelectronics devices will also depend on a detailed understanding of the complex mechanical and thermal of solder joints. Therefore the question of the occurrence of size effects or dimensionally induced constraints, which could change the mechanical properties of solder joints in small dimensions dramatically, came into focus of investigation. Tensile tests were performed to investigate the influence of joint size on the tensile strength and fracture strain. Strains across the solder joint were measured using a non-contacting laser speckle sensor. Scanning electron microscopy (SEM) was used to analyze the complex modes of fracture and crack propagation in the solder interconnect. The variation of the gap size influenced also the crack growth behavior. The observed behavior can be interpreted in terms of an existing theory for brazed joints to complement Finite Element Analysis that is usually used for a description of these phenomena.

High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes

Abstract: In this paper, an innovative active-quenching and recharging circuit for single-photon avalanche diodes is presented. The proposed driver is very fast and extremely compact. It is based on a novel quenching paradigm that heavily reduces dead time, which now is only limited by the sensor rather than the circuit itself. To test speed performance, we designed the circuit with a dielectrically insulated 2-mum technology supplied by ST Microelectronics and carried out postlayout simulations using SPECTRE. Moreover, the functionality of the circuit was also validated with experimental measurements on a medium scale integration (MSI) discrete implementation.

Temporary Bonding and DeBonding Enabling TSV Formation and 3D Integration for Ultra-thin Wafers

Abstract: As the microelectronics industry promotes emerging and future applications, new and improved methods will be necessary to meet the manufacturing challenges associated with new products and processes. Emerging products and applications such as heterogeneous integrated chips (3D, TSV-through silicon via), radio-frequency identification tags, ever denser memory devices along with the advent of new advanced packaging technologies for a variety of products ranging from logic to memory to image sensors (CIS) require increasingly thinner substrates. While thin (<100 mum) silicon wafers exhibit increased flexibility, which in some cases is actually desired, such wafers also exhibit increased instability and fragility. The increased degree of fragility becomes even more pronounced in compound semiconductor wafers because of the mechanical properties of the constituent materials. The lack of mechanical stability and the increased fragility present a major challenge to maintaining high yield levels in volume manufacturing environments. A reliable support and handling solution is needed to overcome the above-mentioned challenges while maintaining yield levels compatible with low-cost, high-yield manufacturing processes. The solution of choice must enable safe, reliable handling of the substrates through back-thinning and backside processing while being compatible with existing (already installed) equipment lines and manufacturing processes. The most promising and most widely investigated handling solution for UltraThinreg wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via formation, etc. The product wafers can either be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. After completion of the backside processing steps, the product wafer can be released from the carrier wafer and proceed to final packaging processes. This paper will discuss and describe the temporary bonding process step technology, including spin/spray coating process to apply the high performance BrewerScience intermediate adhesive and the subsequent bonding step in detail. The EVG850TB (temporary bonding) equipment and the related process modules to cover this process are explained in addition. Furthermore, backside-processes (like e.g. thinning, backside metallization,.etc) which are typically applied after bonding to form e.g. TSV (through silicon via's) and the corresponding process performance are described. Once the original bonded waferstack went successfully through the backside process steps, debonding will be performed. DeBonding, in this case means, that first the thin wafer is getting debonded via thermally activated slide lift-off approach from the carrier wafer, cleaned in a single wafer cleaning chamber in order to remove the remaining adhesive residuals and than transferred to the dedicated output format. Output formats typically are either filmframe carriers, dedicated wafer cassettes, coin stack packing canisters or e.g. single wafer carriers. The carrier wafer is also getting cleaned and can then be reused again immediately for another bond-process. The EVG850DB (debonding bonding) equipment and the related process modules to cover this process are explained in detail. The paper will conclude with a discussion and comparison of silicon and glass carriers used for temporary bonding with respect to process integration and CoO.

Packaging structure for integration of microelectronics and mems devices by 3d stacking and method for manufacturing the same

Abstract: A packaging structure for integration of microelectronics and MEMS devices by 3D stacking is disclosed, which comprises: an ASIC unit, comprising a first substrate and a circuit layout formed on a surface of the first substrate, wherein a cavity is formed on the other surface and at least a through hole is formed on the ASIC unit; and a MEMS unit, comprising a second substrate and a micro sensor disposed on the second substrate; wherein the micro sensor is disposed in the cavity and there is a conductive material filling the through hole so that the ASIC unit and the MEMS unit can be electrically connected to each other when the ASIC unit is attached onto the MEMS unit.

Laser-machined piezoelectric cantilevers for mechanical energy harvesting

Abstract: In this study, we report results on a piezoelectric- material-based mechanical energy-harvesting device that was fabricated by combining laser machining with microelectronics packaging technology. It was found that the laser-machining process did not have significant effect on the electrical properties of piezoelectric material. The fabricated device was tested in the low-frequency regime of 50 to 1000 Hz at constant force of 8 g (where g = 9.8 m/s2). The device was found to generate continuous power of 1.13 muW at 870 Hz across a 288.5 kOmega load with a power density of 301.3 muW/cm3.

THz Vacuum Microelectronic Devices

Abstract: Compact vacuum devices of output power even at 1W and at terahertz (THz) frequencies above 100GHz offer enormous applications for wide band communication, imaging radars, and spectroscopy. These active vacuum devices are also required in many more unexplored areas of scientific, industrial and medical applications. Such vacuum devices at frequency above 100GHz are very small in dimension and microelectronic technology is needed for their fabrication. Successful development of THz vacuum microelectronic devices therefore needs fusion of vacuum tube technology with the semi-conductor technology. Significant efforts are being carried out worldwide to develop successfully such compact vacuum devices using available LIGA and DRIE semiconductor technologies. This paper presents some details on THz vacuum microelectronic devices.

Sub-micron optical waveguides for silicon photonics formed via the local oxidation of silicon (LOCOS)

Abstract: In this paper we report a novel fabrication technique for silicon photonic waveguides with sub-micron dimensions. The technique is based upon the Local Oxidation of Silicon (LOCOS) process widely utilised in the fabrication of microelectronics components. This approach enables waveguides to be fabricated with oxide sidewalls with minimal roughness at the silicon/SiO2 interface. It is also sufficiently flexible to enable the depth of the oxidised sidewall to be varied to control the polarisation performance of the waveguides. We will present preliminary results on submicron waveguide fabrication and loss characteristics (less than 1 dB/cm), as well as effects of varying waveguide width on modal properties of the waveguides. We consider the ease of fabrication, as well as the quality of the devices produced in preliminary experimental fabrication results, and compare the approach to the more conventional requirements of high resolution photolithographically produced waveguides. We also discuss preliminary optical results, as measured by conventional means. Issues such as the origins of loss are discussed in general terms, as are the fabrication characteristics such as waveguide wall roughness and waveguide profile. We will discuss further work that will help to establish the potential of the technique for future applications.

Investigations of carbon nanotubes epoxy composites for electronics packaging

Abstract: The part of electronics packaging is steadily forced to adapt the requirements of the microelectronic industry. For future electronics application such needs will be: 1) steady miniaturisation of the electronic devices 2) high pin count up to 5000 i / o per device 3) pitches down to 20 mum 4) higher current density per devices 5) higher thermal dissipation loss This is only a small extract of the challenges facing the electronics packaging industry in the future. The aim and duty for electronics packaging is to realize a reliable package for future electronics. Commonplace materials for joining elements like solder are not able to solve these requirements. For example in [1] the authors describe that future IC's operating at high frequencies of 10-28 GHz, signal bandwidths of 20 Gbps and lower supply voltages require an estimated maximum of R (< 10 mOhm), L (<5-10pH) and C (<5-10 fF).[l] Current joining elements can not meet these requirements. To solve these problems the electronics packaging industry researches technologies and materials of the nanotechnology. Especially researches concerning new materials for electronics packaging rise up since the last three years. One of the most researched new materials are Carbon Nanotubes (CNT). Carbon Nanotubes have superior mechanical, electrical and thermal properties. Due to these properties CNT are considered as promising candidates in packaging technology. The most interesting field of application is the use of the Carbon Nanotubes as filler in electrical conductive adhesives. The aim is to improve the performance of conductive adhesives in comparison to common products. This study deals with characterization of carbon nanotube / epoxy adhesives in electronics packaging. For this study we optimize the CNT - adhesive system by modification of the CNT, use of different dispersion technologies and under variation of the epoxy matrix. The resulting adhesives are characterized by measuring their viscosity, mechanical strength and their thermal and electrical conductivity. For all studies Multi Wall Nanotubes were used which can be purchased at a reasonable price. For modification of the CNT they can be treated by low pressure plasma (cvd), UV / ozone treatment or modifiedchemically in solution to achieve a higher polarity resulting in a better dispersibility. Also bonding to the polymer matrix is improved. Success of the processes is studied by XPS and REM. For dispersion technology ultrasonic bath, speed mixing and/or treatment with a roll calander can be used. The polymer matrix is also varied in order to achieve an appropriate viscosity at the CNT-content of interest that enables good results in screen printing. Also CNT-polymer interaction can be adapted by varying polarity of the resin used. The distribution of CNT in the matrix is studied by TEM. The first investigations show that ultrasonic finger is the favourable dispersion technology to achieve well dispersed CNT. For modification of the CNT the plasma treatment came out to be efficient to give appropriate amounts of hydroxyl groups.

Joining microelectronics and microionics: Nerve cells and brain tissue on semiconductor chips

Abstract: The direct electrical interfacing of semiconductor chips with individual nerve cells and with brain tissue is considered. At first, the structure of the cell–chip contact is described and then the electrical coupling is characterized between ion channels, the electrical elements of nerve cells, and transistors and capacitors of silicon chips. On that basis, the signal transmission between microelectronics and microionics is implemented in both directions. Simple hybrid systems are assembled with neuron pairs and with small neuronal networks. Finally, the interfacing with capacitors and transistors is extended to brain tissue on silicon. The application of CMOS chips with capacitively coupled recording sites allows an imaging of neuronal activity with high spatiotemporal resolution. Goal of the work is an integration of neuronal network dynamics and digital electronics on a microscopic level for applications in brain research, medical prosthetics and information technology.

RTD-based smart temperature sensor: Process development and circuit design

Abstract: Planar resistance temperature detector, RTD, can be manufactured with microelectronics processing techniques. However, the manufactured planar resistor requires an extra step for adjustment of the 0degC reference resistance, R 0. In this paper, we have evaluated the fabrication of nickel-RTD transducers for smart temperature sensors. By applying the smart sensor concept, the resistance adjustment step is avoided, as the calibration curve can be stored in the Transducer Electronics Datasheet (TEDS). The RTDs have been fabricated by thermal evaporation of nickel onto an alumina substrate. Calibration curves have been measured as a function of temperature, and a high linearity is observed. Two different prototypes for the conditioning and processing electronics are analyzed.

Silicon Nanoparticles. New Photonic and Electronic Material at the Transition Between Solid and Molecule

Abstract: Unlike bulk silicon, a spectacularly dull material, ultrasmall silicon nanoparticles are spectacularly efficient at emitting light in RGB colours. In addition to being ultrabright, reconstituted films of particles exhibit stimulated emission. Light-emitting Si devices could eventually result in a laser on a chip, new generation of Si chips, and extend the functionality of Si technology from microelectronics into optoelectronics and biophotonics. We present in this review experimental as well as theoretical and simulations results discussing the synthesis, structure, and the wide-ranging optical, electronic, mechanical and (derivatized) biocompatible properties and applications of the particles. We discuss the basic mechanism behind the multi-novel properties in terms of silicon–hydrogen configurations of filled fullerene. With a tetrahedral core and a strong molecule-like reconstruction of the surface, the particles constitute a new phase or “supermolecule” that exhibits solid-like behaviour as well as molecule-like behaviour.

Atomic-scale silicon device fabrication

Abstract: The driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce device sizes below 10 nm. In this paper we demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity crystal growth. Using this process we have fabricated conducting nanoscale wires with widths down to ∼8 nm, and arrays of P-doped dots in silicon. We will present an overview of devices that have been made with this technology and highlight some of the detailed atomic level understanding of the doping process developed towards atomically precise devices.