Showing papers on "Mixed-signal integrated circuit published in 1996"
TL;DR: In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high speed potential of advanced Si-bipolar technologies, starting from the most promising circuit concepts and an adequate resistance level, the dimensions of individual transistors in the IC's must be optimized very carefully using advanced transistor models.
Abstract: In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.
284 citations
Book•
01 Nov 1996
TL;DR: Jaeger as mentioned in this paper presents a much more balanced coverage of analog and digital circuits, integrating the author's extensive industrial backround in precision analog-and digital design with his many years of experience in the classroom.
Abstract: This preview guide presents the first 10 chapters of the our new title by Richard Jaeger: Microelectronic Circuit Design. This cutting edge new text develops a comprehensive understanding of the basic techniques of modern electronic circuit design, analog and digital, discrete and integrated. Digital electronics has evolved to be an extremely important area of circuit design, but it is included almost as an after-thought in the majority of introductory electronics texts. This book presents a much more balanced coverage of analog and digital circuits. The writing integrates the author's extensive industrial backround in precision analog and digital design with his many years of experience in the classroom.
260 citations
15 May 1996
TL;DR: This chapter covers device and circuit aspects of low-power analog CMOS circuit design, with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.
Abstract: This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. Low-current biasing also has a strong influence on noise and matching properties. All these issues are discussed, together with the particular aspects related to passive devices and parasitic effects. The design process has to be supported by efficient and accurate circuit simulation. To this end, the EKV compact MOST model for circuit simulation is presented. The use of the basic concepts such as pinch-off voltage, inversion factor and specific current are highlighted thanks to some very simple but fundamental circuits and to an effective use of the model. New design techniques that are appropriate for low-power and/or low-voltage circuits are presented with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.
178 citations
28 Apr 1996
TL;DR: The validity of the proposed test method has been verified throughout some examples such as operational amplifiers and analog-to-digital converter (ADC), which imply that oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing.
Abstract: A new low-cost test method for analog integrated circuits, called oscillation-test, is presented. During the test mode, the circuit under test (CUT) is converted to a circuit that oscillates. Faults in the CUT which cause a reasonable deviation of the oscillation frequency from its nominal value can be detected. Using this test method, no test vector is required to be applied. Therefore, the test vector generation problem is eliminated and the test time is very small because a limited number of oscillation frequencies is evaluated for each CUT. Due to its digital nature, the oscillation frequency can be easily interfaced to boundary scan. This characteristics imply that oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing. In this paper, the validity of the proposed test method has been verified throughout some examples such as operational amplifiers and analog-to-digital converter (ADC).
171 citations
TL;DR: A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage and applies these fast techniques to the verification of large mixed-signal circuits.
Abstract: This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage. Truncated series expansions of the analytical impedance model are used to accelerate solution of the resulting boundary element equations. A methodology that applies these fast techniques to the verification of large mixed-signal circuits and results that confirm its efficiency are described. This complete methodology has been applied to the design and verification of an industrial mixed-signal video analog-to-digital converter IC for substrate noise problems.
120 citations
TL;DR: Analog and mixed-signal integrated circuits are also susceptible to single-event effects, but they have rarely been tested as discussed by the authors, thus, they require modified test techniques and data analysis.
Abstract: Analog and mixed-signal integrated circuits are also susceptible to single-event effects, but they have rarely been tested. Analog circuit single-particle transients require modified test techniques and data analysis. Existing work is reviewed and future concerns are outlined.
81 citations
TL;DR: In this paper, a back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application and a cost-effective low power, lowvoltage, high density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.
Abstract: The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process have been set up against latch-up, parasitic bipolar, impact ionization, and stand by current. Following these guidelines, a cost-effective low power, low-voltage, high-density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.
81 citations
10 Feb 1996
TL;DR: Design techniques for 1.2 V CMOS switched-capacitor (SC) circuits are described and the signal paths are fully differential to maximize noise immunity against disturbances from supplies and substrate, critical when a large number of digital circuits are on the same chip.
Abstract: In battery-powered portable systems, low-voltage CMOS integrated circuits are essential for low power consumption. While integrating analog and digital circuits on the same chip, it is preferred that both analog and digital circuits share the same voltage supplies. However, a low supply voltage forces severe constraints on the design of analog circuits and the conventional CMOS transmission gates may no longer be adequate or even functional as analog switches if the signal swing of the switch control is kept between the nominal supply voltages. Design techniques for 1.2 V CMOS switched-capacitor (SC) circuits are described. MOS transistors with low-threshold voltages are not required. The signal paths are fully differential to maximize noise immunity against disturbances from supplies and substrate, critical when a large number of digital circuits are on the same chip. The analog switches are implemented with nMOS transistors. An on-chip high-voltage generator is used to generate the high-voltage required to turn on the nMOS switches. The circuits use a 0.8 /spl mu/m n-well double-poly double-metal CMOS technology. The threshold voltages are 0.7 V for the nMOSTs, and -0.8V for the pMOSTs.
78 citations
Patent•
13 Feb 1996
TL;DR: In this paper, a digital radio link suitable for transmitting digital voice or data signals includes an input circuit (110) for ATM or equivalent cells, a processing circuit to encapsulate the input cells received by the input circuit with at least error check bits (112) so that detected error can identify a specific cell or group of cells.
Abstract: A digital radio link suitable for transmitting digital voice or data signals includes an input circuit (110) for ATM or equivalent cells, a processing circuit to encapsulate the input cells received by the input circuit with at least error check bits (112) so that detected error can identify a specific cell or group of cells, a digital transmission circuit (fig. 12) for transmitting the encapsulated cells via a wireless link, a reception circuit (fig. 12) for receiving encapsulated cells from an opposite side of the digital radio link, a cell decapsulation and error detection circuit (116) connected to the reception circuit and a cell output circuit (110) for connecting the decapsulation circuit to a digital access circuit (AU).
74 citations
10 Nov 1996
TL;DR: A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented and permits the statistical characterization of large analog and mixed-signal systems.
Abstract: A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principal component analysis, response surface methodology, and statistics to directly calculate the statistical distributions of higher-level parameters from the distributions of lower-level parameters. We have used the methodology to characterize a folded cascode operational amplifier and a phase-locked loop. This methodology permits the statistical characterization of large analog and mixed-signal systems, many of which are extremely time-consuming or impossible to characterize using existing methods.
74 citations
TL;DR: A design tool for simulation of complex integrated optical circuits, based on a professional microwave design system, is developed and a simulation example of an add-drop node using a 4/spl times/4 phased array is presented.
Abstract: A design tool for simulation of complex integrated optical circuits, based on a professional microwave design system has been developed. Implementation of a number of components is described and a simulation example of an add-drop node using a 4/spl times/4 phased array is presented.
TL;DR: It is shown that the noise sampled at the auto-zero mode of the comparator can be used to reconstruct substrate noise waveforms with high resolution, and the influence of noise coupling on analog circuits widely used in on-chip analog-to-digital converters is explained.
Abstract: This paper describes measurement of substrate noise waveforms in mixed-signal integrated circuits. This method uses wide-band chopper-type single-ended voltage comparators as on-chip noise detectors. By analyzing equivalently sampled comparator outputs in synchronized operation, the noise voltage in the auto-zero and compare modes can be measured separately, and noise waveforms were experimentally reconstructed to within 0.5-ns accuracy. The noise transmission path was analyzed, and this showed that the noise sampled at the auto-zero mode of the comparator can be used to reconstruct substrate noise waveforms with high resolution. The results also explain the influence of noise coupling on analog circuits widely used in on-chip analog-to-digital converters.
11 Mar 1996
TL;DR: A method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits and has been implemented in the layout-to-circuit extractor Space.
Abstract: In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract circuits containing many thousands of substrate terminals. Examples are given that show that the method is sufficiently accurate for practical circuit verification. The method has been implemented in the layout-to-circuit extractor Space.
08 Dec 1996
TL;DR: Using dedicated MOSFET matching test structures, this paper demonstrates that performance of analog as well as digital circuit blocks can degrade dramatically in multi level metal CMOS processes when transistors are covered with metal.
Abstract: Using dedicated MOSFET matching test structures, this paper demonstrates that performance of analog as well as digital circuit blocks can degrade dramatically in multi level metal CMOS processes when transistors are covered with metal. An optimized back-end treatment improved the MOSFET matching significantly.
TL;DR: This tutorial describes dynamic testing of analog-to-digital converters using Fourier analysis, including coherent sampling techniques, and introduces frequency domain analysis for the testing of mixed-signal devices.
Abstract: Aimed at design and test engineers making the transition from strictly digital devices to devices with both digital and analog content, this tutorial introduces frequency domain analysis for the testing of mixed-signal devices. The author describes dynamic testing of analog-to-digital converters using Fourier analysis, including coherent sampling techniques. He also covers the challenges of implementing these techniques in a real system and analyzing results to identify problems.
TL;DR: In this paper, the authors review the recent results in analog fault modeling and describe the coming challenges for both industrial and university researchers in the field of mixed-signal integrated circuits.
Abstract: The design and testing of mixed-signal integrated circuits have enjoyed a renaissance in recent years. As is customary with past developments, however, design outpaces testing, and the drive to integrate analog and digital circuits on the same chip exacerbates the test problems. This article reviews the recent results in analog fault modeling-a critical area of mixed-signal testing-and describes the coming challenges for both industrial and university researchers.
TL;DR: This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy and is applicable to both analog and digital circuits.
Abstract: Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.
08 Feb 1996
TL;DR: In this article, the performance of a commercially viable SiGe-HBT technology is demonstrated in analog and digital communications applications, and the measurements show that circuits fabricated in this technology are capable of fulfilling application requirements for RF analog in the 1-5 GHz range and for high-speed digital circuits at or above the 10 Gb/s range, with potentially lower power, lower cost and higher reliability compared to other high speed/RF technology options.
Abstract: The performance of a commercially viable SiGe-HBT technology is demonstrated in analog and digital communications applications. The measurements show that circuits fabricated in this technology are capable of fulfilling application requirements for RF analog in the 1-5 GHz range and for high-speed digital circuits at or above the 10 Gb/s range, with potentially lower power, lower cost and higher reliability compared to other high-speed/RF technology options.
08 Feb 1996
TL;DR: This integrated circuit stores 256 analog voltage levels in high density, non-volatile memory with /spl sim/7.5m V resolution per level with a voltage range of 2.5 V to 5 V.
Abstract: This integrated circuit stores 256 analog voltage levels in high density, non-volatile memory with /spl sim/7.5m V resolution per level. By contrast, the multilevel storage capacity of a typical digital non-volatile memory is 4-level per cell. The integrated circuit operates over a voltage range of 2.5 V to 5.5 V. Previous analog storage implementation use a 5.0 V supply for /spl sim/12 mV equivalent resolution per level in a 128 k EEPROM.
Patent•
11 Apr 1996
TL;DR: In this article, a circuit is provided for selecting one of plurality of integrated circuit chips with a minimum number of chip select signal lines, where each line in each pair provides a logical complementary signal.
Abstract: A circuit is provided for selecting one of plurality of integrated circuit chips with a minimum number of chip select signal lines. A first embodiment includes a plurality of paired address lines; each line in each pair provides a logical complementary signal. Only a selected one of the lines of each pair is coupled to integrated circuit. Each of the integrated circuits is coupled to a unique combination of these selected lines of the pairs. In a second embodiment a select signal is clocked by a controller from one of the integrated circuits to the next in a fashion similar to a shift register. Once the select signal is present in the desired integrated circuit, the controller then provides an enable signal to all the integrated circuits which enables only that desired integrated circuit. In yet another embodiment, the address lines are also used as chip select signal lines, one address line for each integrated circuit. A Chip_select_clock_enable line is used to toggle the chip select signal to the desired device. In a preferred embodiment, a unique value is stored in a register on each integrated circuit. A controller places the unique value of a desired integrated circuit onto a bus. A comparator in each integrated circuit determines which chip has been selected. The controller then provides a chip select signal to activate the desired integrated circuit.
05 May 1996
TL;DR: A methodology is presented for generating compact models of substrate noise injection in complex logic networks and preliminary results demonstrate the validity of the assumptions and the accuracy of the approach on a set of standard benchmark circuits.
Abstract: A methodology is presented for generating compact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation. Assuming spatial independence of all noise generating devices, the cumulative switching noise resulting from all injection patterns is efficiently computed using a gate-level event-driven simulator. The resulting injected signal is then sampled and translated into an energy spectrum which accounts for fundamental frequencies as well as glitch energy. Preliminary results demonstrate the validity of the assumptions and the accuracy of the approach on a set of standard benchmark circuits.
TL;DR: In this article, the authors describe the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite.
Abstract: This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S/sup 2/I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 /spl mu/m standard CMOS process, they demonstrate state-of-the-art performance.
TL;DR: In this paper, the authors present mechanisms for multilevel and mixed-domain simulation of analog systems tied in with mixed analog-digital simulation, and describe the implementation in the form of an open-ended and expandable simulation framework, iMACSIM.
Abstract: Integrated circuit design has evolved to the stage where large, complex, analog and digital functionalities are implemented on a single chip or as an integrated chip set. Besides the mixed signal nature of the designs, the analog sections also include continuous-time and discrete-time components. Thus, for analysis of these integrated modules, all encompassing simulation capabilities are required that address, not only transient analysis of mixed analog-digital circuits, but frequency domain analysis as well. In this paper, we present mechanisms for multilevel and mixed-domain simulation of analog systems tied in with mixed analog-digital simulation. We then describe the implementation in the form of an open-ended and expandable simulation framework, iMACSIM. A simulation backplane is used to provide a general event-processing and scheduling framework that ties together the various algorithms necessary for simulation of various classes of circuits in different analysis regimes.
20 Oct 1996
TL;DR: This work presents a behavioral fault simulation technique for mixed-signal ICs, wherein a robust function approximation method namely regression splines are applied to automatically extract behavioral block parameters.
Abstract: In this work we present a behavioral fault simulation technique for mixed-signal ICs, wherein a robust function approximation method namely regression splines are applied to automatically extract behavioral block parameters. The use of these robust high-level functions enables true behavioral fault simulation while preserving the statistical dependence on the process tolerance. We demonstrate significant speed-up over traditional Monte Carlo methods for two typical mixed-signal circuits, a sigma-delta modulator and a PLL.
Patent•
16 Dec 1996
TL;DR: An integrated circuit package comprising an integrated circuit device and a voltage converter circuit both embedded within the package is described in this paper, where internal conductors on one or more of the layers are configured to connect the components forming the voltage converter circuits.
Abstract: An integrated circuit package comprising an integrated circuit device and a voltage converter circuit both embedded within the package. The voltage converter circuit is configured to convert a standard supply voltage to an operating voltage as required by the integrated circuit device. Also, discrete embedded capacitors may be included to capacitively couple power and ground connections of the integrated circuit device and thus reduce voltage variations during operation of the integrated circuit device. The integrated circuit may package include one or more layers. One or more discrete components or integrated circuits are mounted to one or more layers within the package. Internal conductors on one or more of the layers are configured to connect the components forming the voltage converter circuit. Internal conductors also form connections to the integrated circuit device. The integrated circuit device and voltage converter circuit may be coated with an encapsulant for added protection. The integrated circuit package with embedded voltage converter may be manufactured with processes similar to those used for traditional integrated circuit packages and printed circuit board assemblies.
28 Apr 1996
TL;DR: A novel test generation method for linear analog circuits that employs well established digital test software to generate time-domain tests for analog parametric faults, and target only those stuck-at faults in the digital circuit that could possibly capture parametric failures in the original analog circuit.
Abstract: While analog test generation tools are still in their infancy, the corresponding tools in the digital domain have reached a fair degree of maturity and acceptance. Recognizing this fact, we propose a novel test generation method for linear analog circuits that employs well established digital test software to generate time-domain tests for analog parametric faults. We transform the analog circuit to an equivalent digital circuit, and target only those stuck-at faults in the digital circuit that could possibly capture parametric failures in the original analog circuit. Hence, the sequence of digital test vectors obtained from any test generator represents a test waveform for the analog parametric faults. The technique is illustrated using examples that show this to be a simple, yet attractive alternative to costlier simulation-based analog test generation approaches.
01 Jan 1996
TL;DR: A comparative study of symbolic network analysis methods for analog integrated circuits of practical size indicates that conclusions about the efficiency of the different symbolic analysis methods based upon comparisons for small circuits, can be misleading.
Abstract: A comparative study of symbolic network analysis methods for analog integrated circuits of practical size is presented. The methods are compared with respect to two important criteria: (1) the running time limits of the different algorithms used within every method and (2) the number of terms that are generated needlessly; i.e., generated invalid terms and cancelling terms. The methods are compared for several analog integrated building blocks. The results indicate that conclusions about the efficiency of the different symbolic analysis methods based upon comparisons for small circuits, can be misleading. The study also allows the reader to make a good choice for a symbolic analysis method as the core routine of a modern symbolic analyzer with symbolic simplification capabilities.
08 Feb 1996
TL;DR: A 3.4 V single power supply GaAs single-chip RF transceiver IC for 1.9 GHz digital mobile communication systems such as the Japanese Personal Handy Phone System (PHS) consists of both analog and digital circuits.
Abstract: A 3.4 V single power supply GaAs single-chip RF transceiver IC for 1.9 GHz digital mobile communication systems such as the Japanese Personal Handy Phone System (PHS) consists of both analog and digital circuits. The analog circuits contain a power amplifier (PA), an SPDT switch (SW), two attenuators (ATTs) for transmitting and receiving modes, and a low-noise amplifier (LNA). The digital circuits contain a negative voltage generator (NVG) for single voltage operation and a logic circuit to control the analog circuits and the NVG.
TL;DR: Off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach and the Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits.
Abstract: The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.
01 Jan 1996
TL;DR: In this paper, a short review of the literature on this subject is given, and the requirements for fault modelling and simulation to support supply current test are discussed and some initial results of accelerating this process using macromodelling are presented.
Abstract: Supply current test is well established for digital CMOS circuits and the advantages of improved observability and reliability indication have prompted its use for analogue and mixed signal circuits. A short review of the literature on this subject is given. Fault simulation is used for the investigation of dynamic supply current test of a PLL, confirming existing results from smaller circuits that a combination of supply current and output voltage monitoring leads to higher fault coverage. In the paper, fault coverage is further improved, using crosscorrelation of the supply current and output signals, and the potential for BIST implementation of this technique is demonstrated using low resolution polarised crosscorrelation. Fault simulation is also performed on an analogue multiplier to investigate the effect of process parameter deviations on the supply current. The fault coverage is found to be improved by removing the DC component of the signal. Encouraging results are obtained from the application of supply current test techniques to a commercial mixed signal ASIC currently beyond the capabilities of analogue fault simulation, indicating that efforts at improving fault simulation in this area are worthwhile. The requirements for fault modelling and simulation to support supply current test are discussed and some initial results of accelerating this process using macromodelling are presented.