Showing papers on "Operational amplifier published in 2018"
TL;DR: A new structure that can achieve multioctave bandwidth is proposed in this paper together with the design methodology and to verify the validity of the proposed methodology, a multi-octave power amplifier was designed, fabricated, and measured.
Abstract: Total bandwidth of existing wireless communication technologies covers a wide frequency range of over one octave. But most existing power amplifier configurations cannot meet this requirement while at the same time maintaining a high efficiency. Therefore, a new structure that can achieve multioctave bandwidth is proposed in this paper together with the design methodology. The difficulty in realizing a bandwidth larger than one octave lies in the overlapping of fundamental and harmonic frequencies. Regarding this problem, the continuous class-F mode is extended to allow a resistive second harmonic impedance, rather than the pure reactive one. With the relaxed design requirements and overlapping design space of fundamental and second harmonic frequencies, harmonic tuning and fundamental frequency matching networks can be designed separately. More importantly, broadband matching for fundamental frequencies can be implemented simply by considering only three fundamental frequency points using the multiple frequencies matching method. To verify the validity of the proposed methodology, a multioctave power amplifier was designed, fabricated, and measured. Measured results verify a wide bandwidth of 128.5% from 0.5 to 2.3 GHz. Over this frequency range, drain efficiency was larger than 60% with output power greater than 39.2 dBm and large signal gain larger than 11.7 dB.
81 citations
TL;DR: In this article, the authors presented the bandwidth expanding method with wide-temperature range for sense mode coupling dual-mass MEMS gyro, where the real sensing mode of the gyroscope is analyzed to be the superposition of in-phase and anti-phase sensing modes.
54 citations
TL;DR: A method to design low-power low-area active RC filters is presented, allowing the use of single stage topologies for less power consumption and eliminating the compensation capacitor.
Abstract: A method to design low-power low-area active RC filters is presented. The output voltages of the operational amplifiers are scaled and buffered, allowing the use of single stage topologies for less power consumption and eliminating the compensation capacitor. Tuning of the filter characteristic is also done by switching the currents through the output buffers, which removes the need for capacitor banks. The advantages of the proposed method are incorporated to present a general low-power biquad with small die area. The biquad section is then used to design a low-power baseband filter for Bluetooth receivers with 600-KHz cutoff frequency. The fourth-order filter, fabricated in a 0.18- $ {\mu }\text{m}$ CMOS process, consumes 0.5 mW with a die area of 0.13 mm $^{2}$ .
40 citations
TL;DR: The results of the study reveal that the designed neuromorphic circuits, along with the proposed A/D and D/A converters, provide an average power saving of over the ASIC implementation in a 90-nm CMOS technology.
Abstract: In this paper, we propose an ultra low-power analog neuromorphic circuit to be trained to process sensory data in the Internet of Things smart sensors where low-power and area-efficient computing is required To reduce the operating voltage of the circuit while maintaining the performance, we focus on designing a memristive neuromorphic circuit without employing operational amplifiers Therefore, we use the CMOS inverters as the neurons in our memristive neuromorphic circuit We also propose ultra low-power mixed-signal input/output interfaces to make the circuit connectable to other digital components such as embedded processor To assess the efficacy of the proposed circuit and its interfaces which include memristive neural network based A/D and D/A converters, HSPICE simulations are utilized The results indicate that at the operating voltage of ±025 V, at least $108 \times $ ( $278 \times $ ) reduction in the power consumption of the output (input) interface compared to that of the conventional structures is achieved Additionally, the effectiveness of the neuromorphic circuit enhanced by the proposed interfaces is evaluated under some applications such as image recognition, human behavior analysis, and air quality predictions The results of the study reveal that the designed neuromorphic circuits, along with the proposed A/D and D/A converters, provide an average power saving (speedup) of $2960 \times $ ( $37 \times $ ) over the ASIC implementation in a 90-nm CMOS technology
37 citations
TL;DR: Fractional-order memristor emulator circuits can be used for improving future applications such as cellular neural networks, modulators, sensors, chaotic systems, relaxation oscillators, nonvolatile memory devices, and programmable analog circuits.
Abstract: This brief leads the synthesis of fractional-order memristor (FOM) emulator circuits. To do so, a novel fractional-order integrator (FOI) topology based on current-feedback operational amplifier and integer-order capacitors is proposed. Then, the FOI is substituting the integer-order integrator inside flux- or charge-controlled memristor emulator circuits previously reported in the literature and in both versions: floating and grounded. This demonstrates that FOM emulator circuits can also be configured at incremental or decremental mode and the main fingerprints of an integer-order memristor are also holding up for FOMs. Theoretical results are validated through HSPICE simulations and the synthesized FOM emulator circuits can easily be reproducible. Moreover, the FOM emulator circuits can be used for improving future applications such as cellular neural networks, modulators, sensors, chaotic systems, relaxation oscillators, nonvolatile memory devices, and programmable analog circuits.
30 citations
TL;DR: A new NAND-/NOR-gate-based microoperational amplifier (uOP) operating in weak inversion is proposed in this paper and a new fully synthesized, reprogrammable, multistage operational amplifier (OPAMP) array based on the uOP is introduced which provides variable gain and bandwidth depending on the desired performance.
Abstract: This paper presents a fully synthesized 0.4-V analog biquad filter in a 0.13- $\mu \text{m}$ CMOS technology using digital standard cells. In contrast to a custom-designed inverter-based amplifier in the conventional design, a new NAND-/NOR-gate-based microoperational amplifier (uOP) operating in weak inversion is proposed in this paper. Furthermore, by employing feedforward compensation for loop stability, a new fully synthesized, reprogrammable, multistage operational amplifier (OPAMP) array based on the uOP is introduced which provides variable gain and bandwidth depending on the desired performance. As a proof of concept, a second-order switched-R-MOSFET-C analog filter is implemented. All the active blocks in the analog filter, such as the OPAMPs and matched-RC duty-cycle generator, are implemented using digital gates. The filter is realized using Verilog code and synthesized using automated place and route. The prototype IC achieves 77.17-dB-peak spurious free dynamic range and a tunable bandwidth of 1.7–2.5 MHz while consuming only 0.8 mW of power from a 0.4-V analog supply and a 1-V supply for the switches.
29 citations
01 Feb 2018
TL;DR: This paper presents a 2nd-order NS SAR ADC using an error-feedback (EF) structure that highlights the capability of realizing optimized complex NTF zeros by simply using charge sharing summation, a passive SC FIR and a comparator-reused dynamic amplifier with PVT tracking.
Abstract: The noise-shaping (NS) SAR ADC is an emerging hybrid architecture that achieves high resolution and power-efficiency simultaneously by combining the merits of the SAR ADC and the AIADC, making it attractive to sensor readout and healthcare applications. To implement NS, most prior works adopted the classic cascaded integrator feed-forward (CIFF) structure for noise filtering [1-5]. Opamp-based integrators were used in [1-3] to achieve a relatively sharp noise transfer function (NTF), but at the cost of power and scaling friendliness. Reference [4] demonstrated 2nd-order NS using fully passive switched-capacitor (SC) integrators, but has limited NS and thermal noise performance. Reference [5] combines passive SC filters with a dynamic amplifier (D-amp) to achieve good noise and power, but is vulnerable to process-voltage-temperature (PVT) variations. In addition, no prior NS SAR has realized complex NTF zeros for optimum NS. This presents a need for an NS SAR ADC that can combine optimized NTF, power efficiency and PVT robustness. To overcome the limitations of existing work, instead of adopting the CIFF structure, this paper presents a 2nd-order NS SAR ADC using an error-feedback (EF) structure. It highlights the capability of realizing optimized complex NTF zeros by simply using charge sharing summation, a passive SC FIR and a comparator-reused dynamic amplifier with PVT tracking. This work achieves sharp NS performance while maintaining both hardware and power efficiency merits of the NS SAR with improved robustness. The prototype chip, fabricated in 40nm CMOS, achieves a 79dB SNDR at an OSR of 8 using a 9b SAR, resulting in a peak Schreier FoM of 178dB.
28 citations
TL;DR: The proposed circuit reduces the input capacitance of a buffer amplifier while enabling measurements using leads with only two wires, providing a low-complexity and low-cost solution for interference rejection and artifact reduction in dc-coupled dry-contact biopotential measurements.
Abstract: This paper presents a novel two-wired active electrode that achieves ultrahigh input impedance using power supply bootstrapping. The proposed circuit reduces the input capacitance of a buffer amplifier while enabling measurements using leads with only two wires, providing a low-complexity and low-cost solution for interference rejection and artifact reduction in dc-coupled dry-contact biopotential measurements. An implemented prototype shows that, even using standard operational amplifiers, an input capacitance as low as 71 fF can be obtained, maintaining a high impedance in a 0–1 kHz bandwidth, sufficient for ECG, EEG, and EMG measurements. The circuit has a simple and easily replicable implementation that requires no individual adjustment. A common mode rejection ratio (CMRR) above 103 dB at 50 Hz was achieved and the increased rejection to interference due to the potential divider effect was experimentally tested maintaining a 92-dB CMRR at 50 Hz with a 1.2-M $\Omega$ source impedance unbalance. ECG measurements were conducted to validate the active electrode against a traditional alternative, and a test with dry-contact EEG electrodes was successfully conducted. Although the proposed circuit is intended to acquire superficial electrophysiological signals using dry electrodes, it can be used for measurement from other high-impedance sources, such as micropipette electrodes.
27 citations
TL;DR: The proposed OFCC is designed and implemented in both TSMC low-power 90-nm and UMC high-speed 130-nm CMOS technology for use in low-voltage applications and shows promising results.
Abstract: This brief presents a new low-power miniature instrumentation amplifier based on the operational floating current conveyor (OFCC). The OFCC is a general-purpose current mode device capable of realizing all functions as an operational amplifier. The proposed OFCC is designed and implemented in both TSMC low-power 90-nm and UMC high-speed 130-nm CMOS technology for use in low-voltage applications. A single supply of 0.4 V is used to reduce the power consumption. The design utilizes the energy-efficient subthreshold region. A self-cascode technique is used to enhance the tracking capability of the OFCC. Post-layout simulation and Monte Carlo analysis show promising results. The current mode instrumentation amplifier in 90 nm occupies 0.023 mm2 while consuming $11~ {\mu }\text{W}$ with 14 kHz gain-independent bandwidth and common mode rejection ratio (CMRR) of 76 dB. The 130-nm design exhibits input referred noise of $1.1~ {\mu }\text{V}_{\text{RMS}}$ for a bandwidth of 0.07–150 Hz while consuming $14~ {\mu }\text{W}$ and CMRR of 65 dB with 100-kHz bandwidth with chip area 0.021 mm $^{{2}}$ .
26 citations
01 Feb 2018
TL;DR: This work presents a SAR-ISDM ADC with an opamp-less time-domain integrator without gain loss to effectively achieve a 13b resolution at 0.4V supply.
Abstract: With advanced DAC switching [1-3] and low-power comparator [4] techniques, the successive-approximation register (SAR) ADC demonstrates convincing performance with technology development for internet-of-everything (IoE) applications. However, the power efficiency and accuracy of SAR ADCs over 12b are limited by DAC mismatch and comparator noise requirements, which increases by 4x for each additional 1b of resolution. Hybrid-SAR ADCs using sigma-delta modulators (SDMs) for fine conversion have been reported to reduce noise using oversampling and noise shaping operations with a power penalty from the required operational amplifier (opamp) for integrator realization. An integrator using a passive summing technique was reported [5] without using an opamp, however, the resulting gain loss degraded the effective resolution. This work presents a SAR-ISDM ADC with an opamp-less time-domain integrator without gain loss to effectively achieve a 13b resolution at 0.4V supply. An INL splitting (INLS) DAC switching scheme is also developed to achieve the lowest reported switching energy and improve the DNL/INL performance by 4x.
24 citations
TL;DR: This paper combines theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors.
TL;DR: In this paper, the active differential-mode (DM) EMI filter topology for ac/dc converters is investigated and the loop gain and insertion gain of the active filter are derived.
Abstract: In this paper, the active differential-mode (DM) electromagnetic interference (EMI) filter topology for ac/dc converters is first briefly investigated. The active DM EMI filter model was developed based on the models of filter components including a current transformer, a high-pass filter, an operational amplifier, and a class AB amplifier. The system model including the active filter, ac/dc converter, and line impedance stabilization networks (LISNs) are explored. With the developed system model, the loop gain and insertion gain of the active filter are derived. Based on the loop gain, the stability of the active filter is investigated and the compensation is applied to achieve stability and good EMI reduction. Both simulations and experiments are conducted to validate the developed technique.
TL;DR: In this paper, a second-order non-autonomous inductor-free chaotic circuit is presented, which is obtained by introducing a sinusoidal voltage stimulus into the classical Wien-bridge oscillator.
Abstract: The purpose of this paper is to develop a simple chaotic circuit. The circuit can be fabricated by less discrete electronic components, within which complex dynamical behaviors can be generated.,A second-order non-autonomous inductor-free chaotic circuit is presented, which is obtained by introducing a sinusoidal voltage stimulus into the classical Wien-bridge oscillator. The proposed circuit only has two dynamic elements, and its nonlinearity is realized by the saturation characteristic of the operational amplifier in the classical Wien-bridge oscillator. After that, its dynamical behaviors are revealed by means of bifurcation diagram, Lyapunov exponent and phase portrait and further confirmed using the 0-1 test method. Moreover, an analog circuit using less discrete electronic components is implemented, and its experimental results are measured to verify the numerical simulations.,The equilibrium point located in a line segment varies with time evolution, which leads to the occurrence of periodic, quasi-periodic and chaotic behaviors in the proposed circuit.,Unlike the previously published works, the significant values of the proposed circuit with simple topology are inductor-free realization and without extra nonlinearity, which make the circuit can be used as a paradigm for academic teaching and experimental illustraction for chaos.
10 Jul 2018
TL;DR: A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area, and transfer function for the newly proposed solution has been derived and simulation results have been presented.
Abstract: In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2silicon area.
TL;DR: A transconductance-enhancement cascode Miller compensation technique is proposed for low supply-power, large or very large capacitive load multistage amplifiers and both the gain bandwidth and setting time are significantly improved.
TL;DR: This study presents a novel square/triangular wave generator based on multiple-output current follower differential input transconductance amplifier (MO-CFDITA) with reduced complexity in terms of transistors and the practicality of the proposed generator is verified through the experimental results.
Abstract: This study presents a novel square/triangular wave generator based on multiple-output current follower differential input transconductance amplifier (MO-CFDITA) with reduced complexity in terms of transistors. The proposed generator comprises of single MO-CFDITA and one grounded capacitor only which makes the proposed generator circuit suitable to integrated circuit implementation. The proposed generator provides output square wave in current mode and output triangular wave in voltage mode. The amplitude of current-mode square wave is electronically and independently tunable via bias current. The DC level of the triangular wave is also electronically adjustable. The proposed generator has dual-slope operation and its duty cycle is adjustable with the help of DC current source over a range of 5–95%. The proposed generator consumes a power of 1.45 mW only and it is usable up to 50 MHz which is quite good operating frequency range. To examine the performance of the proposed generator, the cadence VIRTUOSO simulation results have been depicted. Additionally, the simulation results and performance parameters of complementary metal–oxide–semiconductor (CMOS) MO-CFDITA are included. The practicality of the proposed generator is verified through the experimental results.
TL;DR: This work shows how to create a synthetic three-stage inducer-input operational amplifier with a fast CRISPR-based differential-input push-pull stage, a slow transcription-and-translation amplification stage, and a fast-enzymatic output stage.
Abstract: Synthetic biology has created oscillators, latches, logic gates, logarithmically linear circuits, and load drivers that have electronic analogs in living cells. The ubiquitous operational amplifier, which allows circuits to operate robustly and precisely has not been built with biomolecular parts. As in electronics, a biological operational-amplifier could greatly improve the predictability of circuits despite noise and variability, a problem that all cellular circuits face. Here, we show how to create a synthetic three-stage inducer-input operational amplifier with a fast CRISPR-based differential-input push-pull stage, a slow transcription-and-translation amplification stage, and a fast-enzymatic output stage. Our "Bio-OpAmp" uses only 5 proteins including dCas9. It expands the toolkit of fundamental analog circuits in synthetic biology and provides a simple circuit motif for robust and precise molecular homeostasis.
TL;DR: Two new op-amp-based multifunction filter structures are proposed which can realize fractional order inverse low pass, high pass and band pass filters and have been simulated in PSPICE and MATLAB to validate the theoretical propositions.
Abstract: Two new op-amp-based multifunction filter structures are proposed which can realize fractional order inverse low pass, high pass and band pass filters. In the first configuration, op-amp is used in an inverting mode while in the second structure op-amp is employed in non-inverting mode. To the best knowledge of the authors, any fractional order inverse filter structure employing any active element/device has not been reported in the open-literature so far. The proposed inverse filters have been simulated in PSPICE using µA741-type op-amp as well as in MATLAB to validate the theoretical propositions.
TL;DR: In this paper, an adjustably transconductance enhanced bulk-driven OTAs working at weak inversion region is presented, based on the traditional positive feedback source degeneration technique, a proposed current-shunt auxiliary amplifier is employed here to modulate the gate of input differential pairs.
Abstract: An adjustably transconductance enhanced bulk-driven operational transconductance amplifier (OTA) working at weak inversion region is presented. Based on the traditional positive feedback source degeneration technique, a proposed current-shunt auxiliary amplifier is employed here to modulate the gate of input differential pairs, achieving a further improvement of the effective transconductance with the CMOS technologies scaling. In addition, an adjustable transconductance enhancement factor is obtained, leading to an enhanced stability performance. Both conventional and proposed bulk-driven OTAs are designed and simulated on CSMC 180 nm process. The simulated results demonstrate that the unity gain-bandwidth of the proposed bulk-driven OTA is improved by 120% compared to that of the conventional counterpart with a little neglected increased power consumption.
TL;DR: The main feature of the proposed CMIA is that unlike most previously reported CMIAs, its CMRR has negligible sensitivity to mismatches.
Abstract: In this paper, analysis and design of a new current-mode instrumentation amplifier (CMIA) circuit is presented. The proposed circuit employs two Current Operational Amplifiers (COA) as active building blocks, one resistor and two transistors operating as variable resistors to electronically control the differential-mode gain. The main feature of the proposed CMIA is that unlike most previously reported CMIAs, its CMRR has negligible sensitivity to mismatches. In addition, in the proposed circuit both active building blocks operate in negative feedback loop which results in an overall enhanced performance. SPICE simulation results using 0.18 μm TSMC CMOS parameters and supply voltage of ±0.9 V show a constant CMRR of about 51 dB regardless of mismatches and wide bandwidth ranging from 14.8 MHz to about 3 MHz for differential-mode gains between 3 and 18 dB, respectively.
TL;DR: This Letter introduces a new circuit topology of the simple electronically controllable voltage-mode bilinear two port (BTP) employing two operational transconductance amplifiers and has a high-impedance input and allows an independent electronic adjusting of zero and pole frequency of the transfer function.
Abstract: This Letter introduces a new circuit topology of the simple electronically controllable voltage-mode bilinear two port (BTP) employing two operational transconductance amplifiers. The proposed two-port circuit is completely resistorless and contains only a grounded capacitor. It has a high-impedance input (a simple cascading of sections is possible) and allows an independent electronic adjusting of zero and pole frequency of the transfer function. The operation of the BTP circuit is demonstrated for two different locations of the pole and zero frequency coordinates. Moreover, a direct application of four BTPs in fractional-order integrators (order -0.11 and -0.33) with phase shifts -10° and -30° is shown. Design specification is verified by experimental measurements.
TL;DR: The results of this research show that the main factor that affecting the noise is en, the feedback resistor (Rf), and junction capacitor in the photodiode (Cj), and the design concept of multi channel TIA (8 channel) using IC Op Amp, with consideration of pin number of each Op Amp and supply needs.
Abstract: VLC is a complex system with lots of challenges in its implementation. One of its problems is noise that originated from internal and external sources (sunlight, artificial light, etc). Internal noise is originated from active components of analog front-end (AFE) circuit, which will be discussed in this paper, especially on the trans-impedance amplifier (TIA) domain. The noise characteristics of AFE circuit in VLC system has been analyzed using the variety of available commercial Op Amp and different types of the photodiode (Si, Si-PIN, Si APD). The approach of this research is based on analytical calculus and simulation using MATLAB®. The results of this research show that the main factor that affecting the noise is en, the feedback resistor (Rf), and junction capacitor in the photodiode (Cj). Besides that, the design concept of multi channel TIA (8 channel) using IC Op Amp, with consideration of pin number of each Op Amp, supply needs, the initial value of Rf, converter to 8-DIP and feedback capacitor (Cf) channel, also discussed in this paper.
18 Jun 2018
TL;DR: A 16-channel bidirectional wireless neural interface with arbitrary-waveform neurostimulators triggered by remote closed-loop analysis of simultaneously recorded neural activity is presented, resulting in a superior 78dB rejection of common-mode (CM) signals and artifacts.
Abstract: We present a 16-channel bidirectional wireless neural interface with arbitrary-waveform neurostimulators triggered by remote closed-loop analysis of simultaneously recorded neural activity. The delta-modulated neural ADC uses no input capacitors and no statically-biased circuits such as opamps, saving both channel area (0.0054mm2) and power (730nW). Delta modulation yields tolerance to input DC offsets of any value, up to the power rail voltage. The differential-difference comparator architecture offers super-GOhm input impedance ensuring that both of the differential inputs transfer functions are well matched, resulting in a superior 78dB rejection of common-mode (CM) signals and artifacts. The highly-oversampling nature of the ADC also renders it insensitive to stimulation artifacts with differential amplitudes of up to 10mV pp , maintaining an ENOB of 9.7 bits and 2.6µV rms integrated input-referred noise. Experimental results validate the key features of the design and include in-vivo recordings in behaving guinea pigs.
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TL;DR: A time-domain analog weighted-sum calculation model is proposed based on an integrate-and-fire-type spiking neuron model that is applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed in each layer and summation results are then fed into the next layers without their subtraction operation.
Abstract: A time-domain analog weighted-sum calculation model is proposed based on an integrate-and-fire-type spiking neuron model. The proposed calculation model is applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed in each layer and summation results are then fed into the next layers without their subtraction operation. We also propose very large-scale integrated (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, the time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can operate with extremely low power consumption. However, they have to use very high resistance devices on the order of G$\rm \Omega$. We designed a proof-of-concept (PoC) CMOS VLSI chip to verify weighted-sum operation with the same weights and evaluated it by post-layout circuit simulation using 250-nm fabrication technology. High resistance operation was realized by using the subthreshold operation region of MOS transistors. Simulation results showed that energy efficiency for the weighted-sum calculation was 290~TOPS/W, more than one order of magnitude higher than that in state-of-the-art digital AI processors, even though the minimum width of interconnection used in the PoC chip was several times larger than that in such digital processors. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000~TOPS/W will be possible. For practical applications, development of emerging analog memory devices such as ferroelectric-gate FETs is necessary.
01 Sep 2018
TL;DR: The original circuit of the Op-Amp and the results of its circuit simulation are given.
Abstract: Features of the design of operational amplifiers (Op-Amp) on complementary field effect transistors with p-n- junction (junction field-effect transistor, JFET) for operation under the influence of penetrating radiation (PR) and extremely low temperatures up to −197°C are considered. The original circuit of the Op-Amp and the results of its circuit simulation are given.
01 Oct 2018
TL;DR: In this article, a new BiJFet array chip (AC) MH2XA030 designed to accelerate the creation of analog integrated circuits (ICs) that retain their performance under the influence of penetrating radiation (the flux of neutrons and fast electrons, the accumulated dose of radiation, the single effects from heavy charged particles) and extremely low temperatures (up to −197°C) is considered.
Abstract: A new BiJFet array chip (AC) MH2XA030 designed to accelerate the creation of analog integrated circuits (ICs) that retain their performance under the influence of penetrating radiation (the flux of neutrons and fast electrons, the accumulated dose of radiation, the single effects from heavy charged particles) and extremely low temperatures (up to −197°C) is considered. The topology of the array chip and its macro cell is described. The schematic design features of radiation-hardened and cryogenic analog ICs based on the AC are indicated. The circuit simulation results of the main analog components of the AC - voltage comparator, two operational amplifiers and two differential difference operational amplifiers are given.
TL;DR: A new complementary metal-oxide-semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study and a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA.
Abstract: A new complementary metal-oxide-semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study Thanks to using the non-conventional quasi-floating-gate (QFG) technique the circuit is capable to work under low-voltage supply of 06 V with extended input voltage range and with class AB output stages The QFG multiple-input metal-oxide-semiconductor transistor is used to reduce the count of the differential pairs that needed to realise the FDDTA with simple CMOS structure The static power consumption of the proposed FDDTA is 40 μW The FDDTA was designed in Cadence platform using 018 μm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA
TL;DR: A super class AB recycling folded cascode operational transconductance amplifier employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads.
Abstract: A super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal.
TL;DR: In this article, a class-AB OTA topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications, where high efficiency is achieved by reusing transistors both for operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages.
Abstract: A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration.
TL;DR: In this article, fundamental design metrics of analog circuits using two-dimensional transition metal dichalcogenide (2D-TMD) molybdenum disulfide (MoS2) transistors are systematically investigated and compared with the state-of-the-art silicon MOSFETs.
Abstract: As the scaling of silicon MOSFET approaches to its physical limit, research efforts have been made in exploring alternative devices. In this work, fundamental design metrics of analog circuits using two-dimensional transition metal dichalcogenide (2D-TMD) molybdenum disulfide (MoS2) transistors are systematically investigated and compared with the state-of-the-art silicon MOSFETs. Based on analytical derivation and numerical simulations, we find that the drain current efficiency and channel length modulation factor of MoS2 transistors are less relevant to the channel length. Under a condition of the same bias current and device geometry, intrinsic gains of MoS2 transistors are at least 12.3 dB higher than silicon MOSFETs. Three case studies are performed to investigate the use of MoS2 transistors in analog circuits. The key performance indicators of operational amplifiers, such as circuit area, power consumption, voltage gain, gain-bandwidth product (GBW), and tolerance to random process variation are studied. Simulation results demonstrate that MoS2 based analog circuits lead to significant improvement in performance and are more resilient to process variation. For example, when designing two-stage common source amplifiers, under an iso-GBW condition, MoS2-based design can increase voltage gain by at least 72%, save circuit area by 45–60%, and reduce power consumption by 11–58% than silicon-based designs.