Showing papers on "Sequential logic published in 2003"

VLSI implementations of threshold logic-a comprehensive survey

Abstract: This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

Designing fault tolerant systems into SRAM-based FPGAs

Abstract: This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. Triple Modular Redundancy (TMR) has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The new technique proposed in this paper was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.

A model for transient fault propagation in combinatorial logic

Abstract: Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional HSPICE like simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a novel mathematical model to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit, which is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to HPSICE. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.

Mechatronics: Electronic Control Systems in Mechanical and Electrical Engineering

Abstract: Preface Introduction 1 Introducing mechatronics Chapter objectives 1.1 What is mechatronics? 1.2 The design process 1.3 Systems 1.4 Measurement systems 1.5 Control systems 1.6 Programmable logic controller 1.7 Examples of mechatronic systems Summary Problems Sensors and signal conditioning 2 Sensors and transducers Chapter objectives 2.1 Sensors and transducers 2.2 Performance terminology 2.3 Displacement, position and proximity 2.4 Velocity and motion 2.5 Force 2.6 Fluid pressure 2.7 Liquid flow 2.8 Liquid level 2.9 Temperature 2.10 Light sensors 2.11 Selection of sensors 2.12 Inputting data by switches Summary Problems 3 Signal conditioning Chapter objectives 3.1 Signal conditioning 3.2 The operational amplifier 3.3 Protection 3.4 Filtering 3.5 Wheatstone bridge 3.6 Pulse modulation 3.7 Problems with signals 3.8 Power transfer Summary Problems 4 Digital signals Chapter objectives 4.1 Digital signals 4.2 Analogue and digital signals 4.3 Digital-to-analogue and analogue-to-digital converters 4.4 Multiplexers 4.5 Data acquisition 4.6 Digital signal processing Summary Problems 5 Digital logic Chapter objectives 5.1 Digital logic 5.2 Logic gates 5.3 Applications of logic gates 5.4 Sequential logic Summary Problems 6 Data presentation systems Chapter objectives 6.1 Displays 6.2 Data presentation elements 6.3 Magnetic recording 6.4 Optical recording 6.5 Displays 6.6 Data acquisition systems 6.7 Measurement systems 6.8 Testing and calibration Summary Problems Actuation 7 Pneumatic and hydraulic actuation systems Chapter objectives 7.1 Actuation systems 7.2 Pneumatic and hydraulic systems 7.3 Directional control valves 7.4 Pressure control valves 7.5 Cylinders 7.6 Servo and proportional control valves 7.7 Process control valves 7.8 Rotary actuators Summary Problems 8 Mechanical actuation systems Chapter objectives 8.1 Mechanical systems 8.2 Types of motion 8.3 Kinematic chains 8.4 Cams 8.5 Gear trains 8.6 Ratchet and pawl 8.7 Belt and chain drives 8.8 Bearings 8.9 Mechanical aspects of motor selection Summary Problems 9 Electrical actuation systems Chapter objectives 9.1 Electrical systems 9.2 Mechanical switches 9.3 Solid-state switches 9.4 Solenoids 9.5 D.C. motors 9.6 A.C. motors 9.7 Stepper motors Summary Problems Microprocessor systems 10 Microprocessors and microcontrollers Chapter objectives 10.1 Control 10.2 Microprocessor systems 10.3 Microcontrollers 10.4 Applications 10.5 Programming Summary Problems 11 Assembly language Chapter objectives 11.1 Languages 11.2 Instruction sets 11.3 Assembly language programs 11.4 Subroutines 11.5 Look-up tables 11.6 Embedded systems Summary Problems 12 C language 12.1 Why C? 12.2 Program structure 12.3 Branches and loops 12.4 Arrays 12.5 Pointers 12.6 Program development 12.7 Examples of programs 12.8 Arduino programs Summary Problems 13 Input/output systems Chapter Objectives 13.1 Interfacing 13.2 Input/output addressing 13.3 Interface requirements 13.4 Peripheral interface adapters 13.5 Serial communications interface 13.6 Examples of interfacing Summary Problems 14 Programmable logic controllers Chapter objectives 14.1 Programmable logic controllers 14.2 Basic PLC structure 14.3 Input/output processing 14.4 Ladder programming 14.5 Instruction lists 14.6 Latching and internal relays 14.7 Sequencing 14.8 Timers and counters 14.9 Shift registers 14.10 Master and jump controls 14.11 Data handling 14.12 Analogue input/output Summary Problems 15 Communication systems Chapter objectives 15.1 Digital communications 15.2 Centralised, hierarchical and distributed control 15.3 Networks 15.4 Protocols 15.5 Open Systems Interconnection communication model 15.6 Serial communication interfaces 15.7 Parallel communication interfaces 15.8 Wireless protocols Summary Problems 16 Fault finding Chapter objectives 16.1 Fault-detection techniques 16.2 Watchdog timer 16.3 Parity and error coding checks 16.4 Common hardware faults 16.5 Microprocessor systems 16.6 Emulation and simulation 16.7 PLC systems Summary Problems System models 17 Basic system models Chapter objectives 17.1 Mathematical models 17.2 Mechanical system building blocks 17.3 Electrical system building blocks 17.4 Fluid system building blocks 17.5 Thermal system building blocks Summary Problems 18 System models Chapter objectives 18.1 Engineering systems 18.2 Rotational-translational systems 18.3 Electromechanical systems 18.4 Linearity 18.5 Hydraulic-mechanical systems Summary Problems 19 Dynamic responses of systems Chapter objectives 19.1 Modelling dynamic systems 19.2 Terminology 19.3 First-order systems 19.4 Second-order systems 19.5 Performance measures for second-order systems 19.6 System identification Summary Problems 20 System transfer functions Chapter objectives 20.1 The transfer function 20.2 First-order systems 20.3 Second-order systems 20.4 Systems in series 20.5 Systems with feedback loops 20.6 Effect of pole location on transient response Summary Problems 21 Frequency response Chapter objectives 21.1 Sinusoidal input 21.2 Phasors 21.3 Frequency response 21.4 Bode plots 21.5 Performance specifications 21.6 Stability Summary Problems 22 Closed-loop controllers Chapter objectives 22.1 Continuous and discrete control processes 22.2 Terminology 22.3 Two-step mode 22.4 Proportional mode 22.5 Derivative control 22.6 Integral control 22.7 PID controller 22.8 Digital controllers 22.9 Control system performance 22.10 Controller tuning 22.11 Velocity control 22.12 Adaptive control Summary Problems 23 Artificial intelligence Chapter objectives 23.1 What is meant by artificial intelligence? 23.2 Perception and cognition 23.3 Reasoning 23.4 Learning Summary Problems Conclusion 24 Mechatronics systems Chapter objectives 24.1 Mechatronic designs 24.2 Case studies 24.3 Robotics Summary Problems and assignments Appendices A The Laplace transform A.1 The Laplace transform A.2 Unit steps and impulses A.3 Standard Laplace transforms A.4 The inverse transform Problems B Number systems B.1 Number systems B.2 Binary mathematics B.3 Floating numbers B.4 Gray code Problems C Boolean algebra C.1 Laws of Boolean algebra C.2 De Morgan laws C.3 Boolean function generation from truth tables C.4 Karnaugh maps Problems D Instruction sets E C library functions F MATLAB and SIMULINK F.1 MATLAB F.2 SIMULINK G Electrical circuit analysis G.1 D.C. circuits G.2 A.C. circuits Further information Answers Index

System of finite state machines

Abstract: A system of finite state machines built with asynchronous or synchronous logic for controlling the flow of data through computational logic circuits programmed to accomplish a task specified by a user, having one finite state machine associated with each computational logic circuit, having each finite state machine accept data from either one or more predecessor finite state machines or from one or more sources outside the system and furnish data to one or more successor finite state machines or a recipient outside the system, excluding from consideration in determining a clock period for the system logic paths performing the task specified by the user, and providing a means for ensuring that each finite state machine allows sufficient time to elapse for the computational logic circuit associated with that finite state to perform its task.

Design methodology for fine-grained leakage control in MTCMOS

Abstract: Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 /spl mu/m, dual V/sub T/ test chip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8/spl times/ measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active configurable logic blocks (CLBs) by up to 2.2/spl times/ (measured) for some CLB configurations.

High-performance and power-efficient CMOS comparators

Abstract: Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.

Garbage in reversible design of multiple output functions

Abstract: In this paper we analyze the number of garbage outputs that must be added to a multiple output function to make it reversible. We give the precise formula for the theoretical minimum. For some benchmark functions, we calculate the garbage required by some proposed reversible design methods and compared it to the theoretical minimum. Based on the information about garbage we suggest a new reversible design method, that produces the minimum number of garbage outputs. Finally, we show that our proposed reversible logic structure may have some application in conventional logic design.

Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization

Abstract: Motivated by the problem of test pattern generation in digital circuits, this paper presents a novel technique called recursive learning that is able to perform a logic analysis on digital circuits. By recursively calling certain learning functions, it is possible to extract all logic dependencies between signals in a circuit and to perform precise implications for a given set of value assignments. This is of fundamental importance because it represents a new solution to the Boolean satisfiability problem. Thus, what we present is a new and uniform conceptual framework for a wide range of CAD problems including, but not limited to, test pattern generation, design verification, as well as logic optimization problems. Previous test generators for combinational and sequential circuits use a decision tree to systematically explore the search space when trying to generate a test vector. Recursive learning represents an attractive alterna- tive. Using recursive learning with sufficient depth of recursion during the test generation process guarantees that implications are performed precisely; i.e., all necessary assignments for fault detection are identified at every stage of the algorithm so that no backtracks can occur. Consequently, no decision tree is needed to guarantee the completeness of the test generation algorithm. Recursive learning is not restricted to a particular logic alphabet and can be combined with most test generators for combinational and sequential circuits. Experimental results that demonstrate the efficiency of recursive learning are com- pared with the conventional branch-and-bound technique for test generation in combinational circuits. In particular, redundancy identification by recursive learning is demonstrated to be much more efficient than by previously reported techniques. In an important recent development, recursive learning has been shown to provide significent progress in design verification problems (22). Also importantly, recursive learning-based techniques have already been shown to be useful for logic optimization. Specifi- cally, techniques based on recursive learning have already yielded better optimized circuits than the well known MIS-11.

Reversible logic synthesis for minimization of full-adder circuit

Abstract: Reversible logic is of the growing importance to many future technologies. A reversible circuit maps each output vector, into a unique input vector, and vice versa. This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the "garbage bit" and number of reversible gates, which is the main challenge of reversible logic synthesis. This proposed full-adder circuit contains only three gates and two garbage outputs whereas earlier full-adder circuit by M. Perkowski et al. (2001) requires four gates and produces two garbage outputs and another existing full-adder circuit by Md. H. H Azad Khan (2002) requires three gates but produces three garbage outputs. Thus, the proposed full-adder circuit is efficient in terms of number of gates with compared to M. Perkowski et al. (2001) as well as in terms of number of garbage outputs with compared to Md. H. H Azad Khan (2002).

System and method for statistical timing analysis of digital circuits

Abstract: The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized random variables while taking correlations into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form.

Low skew clock input buffer and method

Abstract: An input buffer includes first and second cross-coupled differential amplifiers. Each amplifier drives a buffer signal from a first logic state to a second logic state at a first slew rate when an input signal transitions from a first logic state to a second logic state and a complementary input signal transitions from the second logic state to the first logic state, and drives the buffer signal from the second logic state to the first logic state at a second slew rate when the input signal transitions are the complement of these previous transitions. An output circuit generates a first edge of an output signal when the buffer signal from the first amplifier transitions from the first logic state to the second logic state and generates a second edge of the output signal when the buffer signal from the second amplifier transitions from the first to the second logic state.

Simulating resistive bridging and stuck-at faults

Abstract: We present a simulator for resistive bridging and stuck-at faults In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time

Clocked cascading current-mode regulator with high noise immunity and arbitrary phase count

Abstract: A clocked cascadable power regulator including synchronization logic and PWM control logic. The synchronization logic receives a clock signal and asserts a digital output signal synchronized with the clock signal in response to assertion of a digital input signal. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The regulator may be used alone or cascaded with other similar regulators for implementing a multiphase power converter with multiple channels. The clocked cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. In the cascaded configuration, there is one clock common to all channels which ensures that the phase separation between the channels is symmetrical to within the jitter tolerance of the common clock.

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

Abstract: In this paper we present novel recharged logic for multiple-valued (MV) systems by utilizing semi-floating-gate (SFG) transistors. The recharged multiple-valued logic can be used to implement low-power digital circuits. The improvement in power dissipation is mainly in reduced dynamic power dissipation. The main purpose is to level out the power dissipated by a digital system to obtain more suitable logic for mixed mode design.

Logic multiprocessor for FPGA implementation

Abstract: A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.

Timing-driven logic bi-decomposition

Abstract: An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bi-decomposition of Boolean functions and tree-height reduction of Boolean expressions. It is a technology-independent approach that enables one to find tree-like expressions with smaller depths than the ones obtained by state-of-the-art techniques. The approach can also be combined with technology mapping techniques aiming at timing optimization. Experimental results show that new points in the area/delay space can be explored, with tangible delay improvements when compared to existing techniques.

The synthesis of cyclic combinational circuits

Abstract: Digital circuits are called combinational if they are memoryless: they have outputs that depend only on the current values of the inputs. Combinational circuits are generally thought of as acyclic (i.e., feed-forward) structures. And yet, cyclic circuits can be combinational. Cycles sometimes occur in designs synthesized from high-level descriptions. Feedback in such cases is carefully contrived, typically occurring when functional units are connected in a cyclic topology. Although the premise of cycles in combinational circuits has been accepted, and analysis techniques have been proposed, no one has attempted the synthesis of circuits with feedback at the logic level.We propose a general methodology for the synthesis of multilevel combinational circuits with cyclic topologies. Our approach is to introduce feedback in the substitution / minimization phase, optimizing a multilevel network description for area. In trials with benchmark circuits, many were optimized significantly, with improvements of up to 30% in the area. superior to acyclic.We argue the case for radically rethinking the concept of "combinational" in circuit design: we should no longer think of combinational logic as acyclic in theory or in practice, since nearly all combinational circuits are best designed with cycles.

SATORI - A Fast Sequential SAT Engine for Circuits

Abstract: We describe the design and implementation of SATORI-a fast sequential justification engine based on state-of-the-art SAT and ATPG techniques. We present several novel techniques that propel SATORI to a demonstrable 10x improvement over a commercial engine. Traditional sequential justification based on ATPG or, on a bounded model of the sequential circuit using SAT, has diverging strengths and weaknesses. In this paper, we contrast these techniques and describe how their-strengths are combined in SATORI. We use conflict-based learning in each time-frame and illegal state learning across time-frames. This enables both combinational and sequential back-jumping. We experimentally analyze the main features of SATORI by comparing SATORI'S performance against a state-of-the-art SAT solver-ZCHAFF using a bounded model, and a commercial sequential ATPG engine performing justification. Additional results are presented for SATORI versus the commercial ATPG engine and VIS on ISCAS '89 and ITC'99 benchmark circuits for an application to assertion checking.

A design approach to passive interconnects for single flux quantum logic circuits

Abstract: We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.

Integrated circuit with power monitoring/control and device incorporating same

Abstract: A power management integrated circuit for monitoring a parameter of a power system includes: an analog front end operative to receive and at least one of amplify, attenuate and filter analog signals representative of at least one of voltage and current in a power system to produce modified analog signals; an analog to digital converter operative to produce digital signals; the logic coupled with the analog to digital converter operative to receive the digital signals and produce a power parameter and the logic includes a processor core; a random access memory coupled with the logic operative to store the power parameter and the logic is operative to implement a setpoint to detect when the power parameter is outside a determined range; and a digital output coupled with the first logic and the digital output is useable to control a switching circuit outside the power management integrated circuit.

System and method for probabilistic criticality prediction of digital circuits

Abstract: The present invention is a system and method for determining criticality probability of each node, edge and path of the timing graph of a digital circuit in the presence of delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The criticality determination complexity is linear in the size of the graph and the number of sources of variation. The invention includes a method for efficiently enumerating the critical path(s) that is/are most likely to be critical.

Optical logic gates using semiconductor optical amplifiers

Abstract: All-Optical logic can avoid expensive demultiplexing back to electronics in telecommunications. The term all-optical is used to described processing in which all signal paths are optical whether used for control or information. Semiconductor optical amplifiers (SOAs) can perform all optical logic because they have nonlinearity, low latency, and require low power. We use highly accurate computer models to simulate and evaluate NOR and NXOR logic gates using SOAs. These elements can act as building blocks for advanced logic systems. For example, in previous publications we described an approach to constructing arithmetic units form optical logic elements.

Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement

Abstract: The authors propose a scalable abstraction-refinement method for model checking invariant properties on large sequential circuits, which is based on fine-grain abstraction and simultaneous analysis of all abstract counterexamples of the shortest length. Abstraction efficiency is introduced to measure for a given abstraction-refinement algorithm how much of the concrete model is required to make the decision. The fully automatic techniques presented in this paper can efficiently reach or come near to the maximal abstraction efficiency. First, a fine-grain abstraction approach is given to keep the abstraction granularity small by breaking down large combinational logic cones with Boolean network variables (BNVs) and then treating both state variables and BNVs as atoms in abstraction. Second, a refinement algorithm is proposed based on an improved Ariadne's bundle In the legend of Theseus, Ariadne's bundle contained one ball of thread to help Theseus navigate the labyrinth. In this paper, we work with multiple threads-hence, the "improved." of synchronous onion rings on the abstract model, through which the transitions contain all shortest abstract counterexamples. The synchronous onion rings are exploited in two distinct ways to provide global guidance to the abstraction refinement process. The scalability of our algorithm is ensured in the sense that all the analysis and computation required in our refinement algorithm are conducted on the abstract model. Finally, we derive sequential don't cares from the invisible variables and use them to constrain the behavior of the abstract model. We conducted experimental comparisons of our new method with various existing techniques. The results show that our method outperforms other counterexample-guided methods in terms of both run time and abstraction efficiency

Timing optimization of FPGA placements by logic replication

Abstract: Logic replication for placement level timing optimization is studied in the context of FPGAs. We make the observation that critical paths are dominated by interconnect delay and are frequently highly circuitous. We propose a systematic replication technique to "straighten" such paths. The resulting algorithm has several components: cell selection, slot selection for a duplicate cell, fanout partitioning and placement legalization. This algorithm is described and promising preliminary experimental results are reported with up to 29% improvement in critical path delay.

Programmable logic device latch circuits

Abstract: Latch circuitry is provided for programmable logic regions on integrated circuits such as programmable logic device integrated circuits. A programmable logic device may have programmable logic regions based on programmable combinational logic circuits. Latch circuitry in a logic region may be provided between an output of a programmable combinational logic circuit in the logic region and an output of the logic region. When the latch circuitry is enabled, the latch circuitry performs the functions of a level-sensitive latch. When the latch circuitry is disabled, the latch circuitry acts as a passive data path. The passive data path may include only a single driver so that the latch circuitry adds essentially zero additional delay to the data produced by the combinational logic.

Implementation of a new neurochip using stochastic logic

Abstract: Even though many neurochips have been developed and investigated, the best suitable way for implementation has not been known clearly. Our approach is to exploit stochastic logic for various operations required for neural functions. The advantage of stochastic logic is that complex operations can be implemented with a few ordinary logic gates. On the other hand, the operation speed is not so fast since stochastic logic requires certain accumulation time for averaging. However, a huge integration can be achieved and its reliability is high because all of operations are done on digital circuits. Furthermore, we propose a nonmonotonic neuron realized by stochastic logic, since the nonmonotonic property is efficient for the performance enhancement in association and learning. In this paper, we show the circuit design and measurement results of a neurochip comprising 50 neurons are shown. The advantages of nonmonotonic and stochastic properties are shown clearly.