Showing papers on "Static induction transistor published in 2012"

Memory circuit, method of driving the same, nonvolatile storage device using the same, and liquid crystal display device

Abstract: The present invention provides a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a non-volatile storage device that can easily reduce a chip size by using this memory circuit. A memory element 1 is a memory transistor having a transistor structure including a source electrode 14 , a drain electrode 15 , a gate electrode 11 , and, a source region, a drain region, and a channel region made of a metal oxide semiconductor layer 13 . The resistance property between the source and the drain shows a low resistance, and the memory transistor is changed to have an ohmic resistance property, regardless of a voltage application state of the gate electrode, by allowing a writing current with a density not less than a predetermined value to flow in the channel region to generate Joule heat. The memory circuit stores information between a state indicating the ohmic resistance property after the writing and a state indicating a current-voltage characteristic as a transistor depending upon the voltage application state to the gate electrode before the writing.

An all C60 vertical transistor for high frequency and high current density applications

Abstract: We present a vertical organic transistor with high operating frequencies and high current densities based on the organic semiconductor C60. In this vertical organic triode (VOT), doped layers can easily be inserted to efficiently reduce the contact resistance without the need for additional structuring. Combined with annealing at elevated temperatures (150°C for 2 h), we achieve a current density of 1 A/cm2 at a driving voltage of 3 V together with an extremely high transconductance of 30 mS. The transistor retains a voltage gain above 1 up to 1.5 MHz in a simple inverter circuit.

High power semiconductor electronic components with increased reliability

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Power conversion circuit, multiphase voltage regulator, and power conversion method

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

A tunable, dual mode field-effect or single electron transistor

Abstract: A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field-effect transistor is obtained by pinching off a bottom channel with a negative front gate voltage. The gradual transition between these two cases is observed. This dual function uses both vertical and horizontal tunable potential gradients in non-overlapped silicon-on-insulator channel.

Display device, electronic device, and driving method

Abstract: A display device includes data lines and pixels. Each pixel includes a driving transistor, a switch between one of the data lines and a gate of the driving transistor, and a luminescence element connected to the driving transistor. A first circuit path former flows a first test current from the one of the data lines through the first transistor and a second test current from the one of the data lines through the luminescence element. A second circuit path former generates a first voltage and a second voltage in the one of the data lines. The first voltage corresponds to a gate voltage of the first transistor generated by the first test current. The second voltage corresponds to a luminescence voltage of the luminescence element generated by the second test current. A voltage detector detects the first voltage and the second voltage in the one of the data lines.

Semiconductor electronic components with integrated current limiters

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.

Gate control circuit

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

High output current in vertical polymer space-charge-limited transistor induced by self-assembled monolayer

Abstract: We present a promising solution-processed vertical transistor which exhibits high output current, high on/off current ratio, and low operation voltage. Numerous poly(3-hexylthiophene) vertical channels are embedded in vertical nanometer pores. Treating the sidewalls of pores by self-assemble monolayer with long alkyl chains enhances the pore-filling and inter-chain order of poly(3-hexylthiophene). The channel current is therefore greatly increased. A grid metal inside the porous template controls the channel potential profile to turn on and turn off the vertical transistor. Finally, the transistor delivers an output current density as 50–110 mA/cm2 at 2 V with an on/off current ratio larger than 10 000.

Active clamp protection circuit for power semiconductor device for high frequency switching

Abstract: A protection circuit for a power transistor includes a first transistor connected in parallel with the power transistor and having a control terminal connected to a first power supply voltage through a first resistive element; and a first set of diodes connected between a first terminal and a control terminal of the first transistor. In operation, the voltage at the first terminal of the first transistor is clamped to a clamp voltage and the first transistor is turned on to conduct current in a forward conduction mode when an over-voltage condition occurs at a first terminal of the power transistor.

Semiconductor device, manufacturing method and transistor circuit

Abstract: A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor.

Current measurement in a power transistor

Abstract: A circuit arrangement includes a load transistor and a sense transistor. The first load terminal of the load transistor is coupled to the first load terminal of the sense transistor. A measurement circuit comprising a current source configured to provide a calibration current, the measurement circuit configured to measure a first voltage between the first load terminal and the second load terminal of the sense transistor in the on-state of the sense transistor, to determine a resistance of the sense transistor based on the calibration current and the first voltage, to measure a second voltage between the first load terminal and the second load terminal of the load transistor in the on-state of the load transistor, and to determine a load current through the load transistor based on the resistance of the sense transistor and the second voltage.

Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor

Abstract: The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.

Multiphysics Modeling of RF and Microwave High-Power Transistors

Abstract: In this paper, we present a multiphysics approach for the simulation of high-power RF and microwave transistors, in which electromagnetic, thermal, and nonlinear transistor models are linked together within a harmonic-balance circuit simulator. This approach is used to analyze a laterally diffused metal-oxide-semiconductor (LDMOS) transistor that has a total gate width of 102 mm and operates at 2.14 GHz. The transistor die is placed in a metal-ceramic package, with bond-wire arrays connecting the die to the package leads. The effects of three different gate bond-pad layouts on the transistor efficiency are studied. Through plots of the spatial distributions of the drain efficiency and the time-domain currents and voltages across the die, we reveal for the first time unique interactions between the electromagnetic effects of the layout and the microwave behavior of the large-die LDMOS power field-effect transistor.

Switching regulator control circuit, switching regulator, electronic appliance, switching power supply device, and television receiver

Abstract: A high-side variable current source and a high-side transistor are provided in series between a supply power terminal of a control circuit and a gate of a switching transistor. A low-side variable current source and a low-side transistor are provided in series between the gate of the switching transistor and a ground terminal. A slew rate controller controls the current value of at least one of the high-side and low-side variable current sources according to the state of a setting terminal. A switching power supply device has a plurality of output transistors connected in parallel with one another and a controller that generates control signals turning on and off the output transistors at a predetermined frequency so as to generate a desired output voltage from an input voltage and supply the output voltage to a load. The controller determines which output transistor to drive according to the magnitude of the load.

High performance bilayer oxide transistor for gate driver circuitry implemented on power electronic devices

Abstract: The integration of electronically active oxide transistors onto silicon circuits represents an innovative approach to improving the performance of devices. In this paper, we present high performance oxide transistor for use as gate drive circuitry integrated on top of a power electronic device, providing a novel power system. Specifically, as a core device component in gate driver, oxide transistor exhibits remarkable performance such as, high mobility (23∼47cm2/Vs) and high breakdown voltage (BV) of 60∼340V despite low process temperatures (<300°C). In addition, we demonstrate the dynamic behavior of the inverter and the latch produced by oxide transistor and thus a complete and functioning gate drive circuitry can be implemented on top of power management integrated circuit (PMIC) as depicted in the report.

Method for driving semiconductor device

Abstract: A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined potential is held in the node. Data is read out from the memory cell by supplying a precharge potential to a bit line, stopping the supply of the potential to the bit line, and determining whether the potential of the bit line is kept at the precharge potential or decreased.

Semiconductor Device Having Shared Contact Hole and a Manufacturing Method Thereof

Abstract: A semiconductor device has a high-speed circuit and a high-density circuit, each having at least two field effect transistors and two gate electrodes. In the high-speed circuit, a first gate electrode of a first field effect transistor and a second gate electrode of a second field effect transistor are separated by a first pitch. In the high-density circuit, a third gate electrode of a third field effect transistor and a fourth gate electrode of a fourth field effect transistor are separated by a second pitch. The first pitch is larger than the second pitch. Provision of a notch in the third gate electrode of the third field effect transistor in the high-density circuit, at a portion reached by a shared contact hole shared by the third gate electrode and the fourth transistor, increases the contact area between the shared contact hole and an impurity region source/drain of the fourth transistor.

Method and circuit for compensating pixel drift in active matrix displays

Abstract: An apparatus includes a circuit branch electrically connected to a voltage rail and including a light emitting device connected in series with a drain of a dual gate transistor, a switching transistor configured to apply a data voltage to a first gate of the dual gate transistor in response to a scan signal, a capacitor connected between the first gate of the dual gate transistor and the drain of the dual gate transistor, and a conductor for supplying a control voltage to a second gate of the dual gate transistor. A method of operating the circuit is also described.

Bidirectional field effect transistor and method

Abstract: In one embodiment, a structure for a semiconductor device has trench shield electrodes formed above and below a gate electrode. The structure can be configured to function as a bidirectional power field effect transistor.

Pixel circuit, method of driving the same, and organic light emitting display device having the same

Abstract: A method of driving a pixel circuit includes initializing a driving transistor and a storage capacitor by simultaneously applying an initialization voltage and a first power voltage to a gate electrode of the driving transistor and the storage capacitor, respectively, diode-coupling the driving transistor, applying a data voltage to the storage capacitor, applying the data voltage to the gate electrode of the driving transistor by a coupling of a compensation capacitor coupled between the gate electrode of the driving transistor and the storage capacitor, and applying a current corresponding to the first power voltage and the data voltage to an organic light emitting diode that is coupled to the driving transistor.

High-side driver circuit

Abstract: The present invention provides a high-side driver circuit including a power transistor, the first transistor, the second transistor, the second capacitor, the second diode, a start-up circuit. The start-up circuit is coupled between a resistor and the second capacitor to complete a gate driving circuit. And, the aforementioned resistor can either be the gate resistance of the power transistor or an external resistor. The design of start-up circuit enables the functionality of the bootstrap capacitor of being charged to a designate voltage level. Thus, the depletion-mode transistor can be controlled to turn on/off without a floating voltage source or a negative voltage source.

Turn-on spread determines the size of the switching region in an avalanche transistor

Abstract: It has been shown recently that only a small part of the emitter-base interface in a Si bipolar junction transistor participates in short-pulsing avalanche switching. This lateral current shrinkage attributed to the “winner takes all” effect reduces the transistor switching size from 1600 to ∼100 μm, still remaining much larger than the transistor structure thickness. We show using quasi-3-D transient modelling that the size of the operating perimeter, which is critically important for switching efficiency and device reliability, is determined by competition between lateral turn-on shrinkage and spread. The latter has never been demonstrated in avalanche transistors before.

Semiconductor Device and Electronic Device Including Semiconductor Device

Abstract: It is an object to suppress deterioration in characteristics of a transistor in a driver circuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off.

Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material

Abstract: In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.

Bi-fet cascode power switch

Abstract: Power switch devices for high-speed applications are disclosed. The power switch device includes a depletion mode field effect transistor (D-FET), an enhancement mode field effect transistor (E-FET) and a bipolar transistor. In one embodiment, the E-FET is coupled in cascode with the D-FET such that turning off the E-FET turns off the D-FET and turning on the E-FET turns on the D-FET. Furthermore, the bipolar transistor is operably associated with the D-FET and the E-FET such that turning on the bipolar transistor drives current from the D-FET through the bipolar transistor to the E-FET to provide a charge that turns on the E-FET. The bipolar transistor provides several advantages such as a higher Schottky breakdown voltage for the E-FET and faster current switching speed for the power switch device.

Driving method of semiconductor device

Abstract: The semiconductor device includes a transistor and a capacitor element which is electrically connected to a gate of the transistor. Charge held in the capacitor element according to total voltage of voltage corresponding to the threshold voltage of the transistor and image signal voltage is once discharged through the transistor, so that variation in current flowing in the transistor or mobility of the transistor can be reduced.

Logic-based multiple time programming memory cell

Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

A novel 4H–SiC SOI-MESFET with a modified breakdown voltage mechanism for improving the electrical performance

Abstract: In this paper, we present the unique features exhibited by a novel 4H?SiC silicon-on-insulator (SOI) metal?semiconductor field effect transistor (MESFET) in which the active layer consists of an insulator region (ISOI-MESFET). The key idea in this work is to make the dominant breakdown voltage mechanism to be controlled by the channel breakdown and not by the gate breakdown as a result of a high electric field at the edge of the gate near the drain. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. Our simulation results show that the breakdown voltage of the ISOI-MESFET is higher than the conventional bulk-MESFET (CB-MESFET) and conventional 4H?SiC SOI-MESFET (CSOI-MESFET). In this study, we have shown that the saturation current of the proposed structure is larger than the CB-MESFET. Also, the cut-off frequency and maximum oscillation frequency of the ISOI-MESFET improve compared to the CB-MESFET. Therefore, the ISOI-MESFET has superior dc and RF performance compared to the similar device based on the conventional structures.

Dual-gate normally-off nitride transistors

Abstract: A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.