Showing papers on "Voltage-controlled oscillator published in 2006"

Millimeter-wave voltage-controlled oscillators in 0.13-/spl mu/m CMOS technology

Abstract: This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.

Process and Temperature Compensation in a 7-MHz

Abstract: This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25- m, two-poly five-metal (2P5M) CMOS process. Measurements made across a temperature range of 40 C to 125 C and 94 samples collected over four fabrica- tion runs indicate a worst case combined variation of 2.6% (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95% of the sam- ples were found to fall within 0.5% of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was 0.31% for a supply voltage range of 2.4-2.75 V. The clock generator is based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with tem- perature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is de- veloped. The biasing circuit changes the control voltage of the dif- ferential ring oscillator to maintain a constant frequency. A com- parator included at the output stage ensures rail-to-rail swing. The oscillator is intended to serve as a start-up clock for micro-con- troller applications.

A Wide Tuning-Range CMOS VCO With a Differential Tunable Active Inductor

Abstract: By utilizing a differential tunable active inductor for the LC-tank, a wide tuning-range CMOS voltage-controlled oscillator (VCO) is presented. In the proposed circuit topology, the coarse frequency tuning is achieved by the tunable active inductor, while the fine tuning is controlled by the varactor. Using a 0.18-mum CMOS process, a prototype VCO is implemented for demonstration. The fabricated circuit provides an output frequency from 500 MHz to 3.0 GHz, resulting in a tuning range of 143% at radio frequencies. The measured phase noise is from -101 to -118 dBc/Hz at a 1-MHz offset within the entire frequency range. Due to the absence of the spiral inductors, the fully integrated VCO occupies an active area of 150times300 mum2

More on the 1/f2 phase noise performance of CMOS differential-pair LC-tank oscillators

Abstract: This paper presents a rigorous phase noise analysis in the 1/f 2 region for the differential CMOS LC-tank oscillator with both nMOS and pMOS switch pairs. A compact, closed-form phase noise equation is obtained, accounting for the noise contributions from both tank losses and transistors currents, which allows a robust comparison between LC oscillators built with either one or two switch pairs. The fabricated oscillator prototype is tunable between 2.15 and 2.35 GHz, and shows a phase noise of -144 dBc/Hz at 3 MHz offset from the 2.3 GHz carrier for a 4 mA bias current. The phase noise figure-of-merit is practically constant across the tuning range, with a minimum of 191.5 dBc/Hz. A reference single-switch-pair oscillator has been implemented and tested as well, and the difference between the phase noise levels displayed by the two oscillators is very nearly the one expected from theory.

Switched resonators and their applications in a dual-band monolithic CMOS LC-tuned VCO

Abstract: A switched resonator concept, which can be used to reduce the size of multiple-band RF systems and which allows better tradeoff between phase noise and power consumption, is demonstrated using a dual-band voltage-controlled oscillator (VCO) in a 0.18-/spl mu/m CMOS process. To maximize Q of the switched resonator when the switch is on, the mutual inductance between the inductors should be kept low and the switch transistor size should be optimized. The Q factor of switched resonators is /spl sim/30% lower than that of a standalone inductor. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and -123dBc/Hz at a 600-kHz offset and 16-mW power consumption. Compared to a single-band 1.8-GHz VCO, the dual-band VCO has almost the same phase noise and power consumption, while occupying /spl sim/37% smaller area.

A Spectral Model for RF Oscillators With Power-Law Phase Noise

Abstract: In this paper, we apply correlation theory methods to obtain a model for the near-carrier oscillator power-spectral density (PSD). Based on the measurement-driven representation of phase noise as a sum of power-law processes, we evaluate closed form expressions for the relevant oscillator autocorrelation functions. These expressions form the basis of an enhanced oscillator spectral model that has a Gaussian PSD at near-carrier frequencies followed by a sequence of power-law regions. New results for the effect of white phase noise, flicker phase noise and random walk frequency modulated phase noise on the near-carrier oscillator PSD are derived. In particular, in the case of 1/f phase noise, we show that despite its lack of stationarity it is possible to derive a closed form expression for its effect on an oscillator PSD and show that the oscillator output can be considered to be wide-sense stationary

More on the $1/{\rm f}^{2}$ Phase Noise Performance of CMOS Differential-Pair LC -Tank Oscillators

Abstract: This paper presents a rigorous phase noise analysis in the 1/f2 region for the differential CMOS LC-tank oscillator with both nMOS and pMOS switch pairs. A compact, closed-form phase noise equation is obtained, accounting for the noise contributions from both tank losses and transistors currents, which allows a robust comparison between LC oscillators built with either one or two switch pairs. The fabricated oscillator prototype is tunable between 2.15 and 2.35 GHz, and shows a phase noise of -144 dBc/Hz at 3 MHz offset from the 2.3 GHz carrier for a 4 mA bias current. The phase noise figure-of-merit is practically constant across the tuning range, with a minimum of 191.5 dBc/Hz. A reference single-switch-pair oscillator has been implemented and tested as well, and the difference between the phase noise levels displayed by the two oscillators is very nearly the one expected from theory

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

Abstract: In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered

A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator

Abstract: A time-based analog-to-digital converter(ADC) employing a multi-phase voltage-controlled oscillator(VCO) is presented. The VCO is based on a ring oscillator which converts analog input voltage to phase information. Digital output is produced by a phase quantizer which consists of a counter for coarse quantization and phase detector for fine quantization. Using this technique, an 8-bit 100Msamples/s ADC is designed and simulated. Impact of jitter and VCO linearity on the ADC performance is analyzed and verified.

Tail Current-Shaping to Improve Phase Noise in LC Voltage-Controlled Oscillators

Abstract: This paper introduces a tail current-shaping technique in LC-VCOs to increase the amplitude and to reduce the phase noise while keeping the power dissipation constant The tail current is made large when the oscillator output voltage reaches its maximum or minimum value and when the sensitivity of the output phase to injected noise is the smallest; the tail current is made small during the zero crossings of the output voltage when the phase noise sensitivity is large The phase noise contributions of the active devices are decreased and the VCO has a larger oscillation amplitude and thus better DC to RF conversion compared to a standard VCO with equal power dissipation A circuit design to implement tail current-shaping is presented that does not dissipate any extra power, does not use additional (noisy) active devices and occupies a small area The operation and performance of the presented circuit is extensively analyzed and compared to an ideal pulse biased technique The presented analysis is confirmed by measurement results of two 2-GHz differential nMOS VCOs fabricated in 025-mum BiCMOS process

Verifying analog oscillator circuits using forward/backward abstraction refinement

Abstract: Properties of analog circuits can be verified formally by partitioning the continuous state space and applying hybrid system verification techniques to the resulting abstraction. To verify properties of oscillator circuits, cyclic invariants need to be computed. Methods based on forward reachability have proven to be inefficient and in some cases inadequate in constructing these invariant sets. In this paper, we propose a novel approach combining forward- and backward-reachability while iteratively refining partitions at each step. The technique can yield dramatic memory and runtime reductions. We illustrate the effectiveness by verifying, for the first time, the limit cycle oscillation behavior of a third-order model of a differential VCO circuit.

A 60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise Reduction

Abstract: An on-chip resonator with artificial dielectric in place of the LC tank yields reduced metal/substrate losses, higher resonator Q and alambda/4 length reduction of 4.7 times. The VCO uses 90nm CMOS, with 0.015mm2 area, consumes 1.9mW and has a measured phase noise of -100dBc/Hz at 1MHz offset. The FOM is -193dBc/Hz

Micromachined CMOS LNA and VCO by CMOS-compatible ICP deep trench technology

Abstract: Selective removal of the silicon underneath the inductors in RF integrated circuits based on inductively coupled plasma (ICP) deep trench technology is demonstrated by a complementary metal-oxide-semiconductor (CMOS) 5-GHz low-noise amplifier (LNA) and a 4-GHz voltage-controlled oscillator (VCO). Design principles of a multistandard LNA with flat and low noise figures (NFs) within a specific frequency range are also presented. A 2-dB increase in peak gain (from 21 to 23 dB) and a 0.5-dB (from 2.28 to 1.78 dB) decrease in minimum NF are achieved in the LNA while a 3-dB suppression of phase noise is obtained in the VCO after the ICP backside dry etching. These results show that the CMOS-process-compatible backside ICP etching technique is very promising for system-on-a-chip applications.

A regulated charge pump with small ripple voltage and fast start-up

Abstract: A regulated charge pump circuit is realized in a 3.3-V 0.13-/spl mu/m CMOS technology. The charge pump exploits an automatic pumping control scheme to provide small ripple output voltage and fast start-up by decoupling output ripple and start-up time. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. The former automatically adjusts the size of pumping driver to reduce ripple voltage according to output voltage. The latter changes the pumping period by controlling a voltage-controlled oscillator (VCO). The output frequency of the VCO varies from 400 kHz to 600 kHz by controlling the input bias voltage of the VCO. The prototype chip delivers regulated 4.5-V output voltage from a supply voltage of 3.3 V with a flying capacitor of 330 nF, while providing 30 mA of load current. The area is 0.25 mm/sup 2/ and the measured output ripple voltage is less than 33.8 mV with a 2-/spl mu/F load capacitor. The power efficiency is greater than 70% at the range of load current from 1 to 30 mA. An analytical model for ripple voltage and recovery time is proposed demonstrating a reasonable agreement with SPICE simulation results.

A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver

Abstract: This paper describes the design and performance of the first tri-band (2100, 1900, 800/850 MHz) single-chip 3G cellular transceiver IC for worldwide use. The transceiver has been designed to meet all narrowband blocker, newly proposed Adjacent Channel II, and Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The design is part of a reconfigurable reference platform for multi-band, multi-mode (GSM/EDGE + WCDMA) radios. The zero-IF receiver is comprised of a novel multi-band quadrature mixer, seventh-order baseband filtering, and a novel DC offset correction scheme, which exhibits no settling time or peak switching transients after gain steps. The receiver lineup is designed to optimize HSDPA throughput and minimize sensitivity to analog baseband filter bandwidth variations. The direct-launch transmitter is made up of a third-order baseband filter, an I/Q modulator with variable gain, an integrated transformer, an RF variable gain amplifier, and a power amplifier driver. At +9.5-dBm output power, the transmitter achieves an error vector magnitude (EVM) of 4%. Fractional-N synthesizers achieve fast lock times of 50 /spl mu/s (150 /spl mu/s) within 20 ppm (0.1 ppm). Automatically calibrated, integrated VCOs achieve a 1.6-GHz tuning range to facilitate coverage over all six 3GPP frequency bands. The IC draws 34 mA in receive (18-mA receiver plus 16-mA fractional-N PLL/VCO) and 50 to 62 mA in transmit (-76 dBm to +9.5 dBm), including PLL/VCO, using a 2.775-V supply voltage. The RF transceiver is integrated with the baseband signal processing and associated passives in a 165-pad package, resulting in the first tri-band 3G radio transceiver with a digital interface which requires no external components.

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

Abstract: This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC tank oscillator providing a compact and low-power solution compatible with low-voltage technologies. A 0.13-mum CMOS prototype tailored to the GPS application is presented. The experimental results exhibit a noise figure of 4.8 dB, a gain of 36 dB, an IIP3 of -19 dBm with a total power consumption of only 5.4 mW from a voltage supply of 1.2 V

192 GHz push–push VCO in 0.13 [micro sign]m CMOS

Abstract: A 192 GHz cross-coupled push-push voltage controlled oscillator (VCO) is fabricated using the UMC 013 /spl mu/m CMOS logic process The VCO can be tuned from 1914 to 1927 GHz The VCO provides output power of /spl sim/-20 dBm and phase noise of /spl sim/-100 dBc/Hz at 10 MHz offset, while consuming 11 mA from a 15 V supply

On the amplitude and phase errors of quadrature LC-tank CMOS oscillators

Abstract: An analytic approach for the estimation of the phase and amplitude imbalances caused by component mismatches and parasitic magnetic fields in two popular quadrature LC oscillators is presented. Very simple and closed-form equations are derived, proving that, although the two topologies share the same small signal circuit, they display very different sensitivities to the mentioned sources of imbalance. Moreover, it is shown that parasitic inductors coupling, overlooked up to date, plays a key role ultimately limiting the achievable phase accuracy. The theoretical results are verified through extensive simulations and measurements on a 1.7-GHz quadrature oscillator and frequency up-converter implemented in a 0.18-/spl mu/m CMOS process.

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

Abstract: This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance

A 140-GHz fundamental mode voltage-controlled oscillator in 90-nm CMOS technology

Abstract: Fundamental mode voltage-controlled oscillators in F-band (90-140GHz) were fabricated using the UMC 90-nm logic CMOS process. The maximum operating frequencies of these three oscillators are 110, 123, and 140GHz, respectively. The 140-GHz voltage controlled oscillator provides -22 to -19-dBm output power, a frequency tuning range of 1.2GHz and phase noise of -85dBc/Hz at 2-MHz offset from the carrier, while consuming 8mA from a 1.2-V supply

A low-phase-noise K-band CMOS VCO

Abstract: A novel circuit topology for low-phase-noise voltage controlled oscillators (VCOs) is presented in this letter. By employing a PMOS cross-coupled pair with a capacitive feedback, superior circuit performance can be achieved especially at higher frequencies. Based on the proposed architecture, a prototype VCO implemented in a 0.18-mum CMOS process is demonstrated for K-band applications. From the measurement results, the VCO exhibits a 510-MHz frequency tuning range at 20GHz. The output power and the phase noise at 1-MHz offset are -3dBm and -111dBc/Hz, respectively. The fabricated circuit consumes a dc power of 32mW from a 1.8-V supply voltage

Single chip gsm/edge transceiver architecture with closed loop power control

Abstract: A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.

An RF-powered, wireless CMOS temperature sensor

Abstract: We present a wireless, fully integrated CMOS temperature sensor that recovers power from a radio frequency (RF) signal, and returns data as a frequency-modulated 2.3-GHz signal to a base station. Power is recovered from a 450-MHz incident signal with the help of a low-threshold, high-efficiency, voltage rectifier-multiplier circuit. This technique decreases the minimum incident RF power required, compared to state-of-the-art wirelessly powered telemetry systems. The rectifier-multiplier can collect energy from a base station placed up to 18 m away. To further increase the range from the base, the device collects energy in a low power standby/charging mode. A mode selector circuit monitors the amount stored energy and decides if the system is transmitting data or is in the standby/charging mode. A bootstrapped reference generates a complementary to absolute temperature (CTAT) voltage with an R-squared regression of 0.9995 to a linear fit. This reference is used as the temperature sensor of the system, controlling a low-power, integrated, voltage-controlled LC oscillator (VCO). The oscillation frequency of the VCO is modulated by ambient temperature changes. The modulated carrier is transmitted by a fully integrated power amplifier. A temperature sensitivity of 126 ppm/degC is achieved and the entire sensor consumes 1.1 mA while transmitting data

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

Abstract: A 20-GHz phase-locked loop with 49 ps/sub pp//065 ps/sub rms/ jitter and -1135 dBc/Hz phase noise at 10-MHz offset is presented A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -440 dBc A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range The phase-locked loop fabricated in a 013-/spl mu/m CMOS operates from 176 to 194GHz and dissipates 480mW

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning

Abstract: This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-mum CMOS process, the PLL occupies 0.15 mm2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms

An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback

Abstract: A fully integrated 0.024mm2 differentially tuned 6GHz LC VCO for 6+Gbps high speed serial (HSS) links in a 90nm bulk CMOS is presented. It is smaller than any LC-VCO reported to date at this frequency. Its size is comparable with ring oscillators but it has significantly better phase noise. A circuit technique is introduced to dynamically set the common-mode (CM) voltage of the differential varactor control signals equal to the VCO?s CM. Using a differential control a very wide tuning range from 4.5GHz to 7.1GHz (45%) is achieved. The VCO has a measured phase noise of -117.7dBc/Hz at a 3MHz offset from a 5.63GHz carrier while dissipating 14mW from a 1.6V supply.

A low phase-noise CMOS VCO with harmonic tuned LC tank

Abstract: This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangular-shaped voltage at the switching differential cell, which effectively maximizes the slope of the switching cell output voltage at a zero crossing point. In addition, the proposed technique also suppresses the down-conversion of the noise around the second harmonic frequency by the second harmonic short of the tank. One second HT VCO and two third HT VCOs are designed and implemented to evaluate the concept using a 0.35- and 0.13-/spl mu/m CMOS process. The figure-of-merit (FOM) of the second HT VCO, third HT VCO1, and third HT VCO2 are -180.7, -183.7, and -189.5, respectively. The best FOM performance of the VCO has phase noises of -100.4, -132.0, and -140.8dBc/Hz at 100-kHz, 1-MHz, and 3-MHz offset frequencies at the 2-GHz carrier, respectively. This VCO consumes 3.29 mA from a 1.8-V supply with the silicon area of 500 /spl mu/m/spl times/750 /spl mu/m.

Direct ZVS start-up of a current-fed resonant inverter

Abstract: Zero voltage switching (ZVS) is critical for reliable operation of standard current-fed parallel resonant inverters. Under steady-state conditions, ZVS can be achieved using common techniques such as a phase lock loop, a voltage controlled oscillator, and other integral controllers. However, during transient processes, achieving ZVS is not trivial for such controllers and consequently switch failure can occur. This paper proposes a dynamic ZVS method to solve the start-up problems by using a forced dc current. Start-up conditions are analyzed and complete dynamic ZVS control is achieved. If the ramp-up delay of practical dc power supplies is utilized, the start-up process can be controlled to be overshoot-free at no extra cost. The validity of this method is proven using both PSpice simulations and experimental results

Frequency Scaling and Topology Comparison of Millimeter-wave CMOS VCOs

Abstract: This paper presents an algorithmic design methodology and frequency scaling technique for CMOS VCOs. It illustrates the almost ideal scaling of a fundamental 10-GHz, 90-nm CMOS Colpitts VCO with ?117 dBc/Hz phase noise and 4 dBm output power to 77 GHz. The 77-GHz VCO features linear 8.3% tuning range and a phase noise of ?100.3 dBc/Hz at 1 MHz offset. The first complementary cross-coupled VCO operating at 77 GHz is also reported. In addition, a new figure of merit for CMOS VCO based on the one defined in the 2003 ITRS is proposed to adequately account for the VCO output power and efficiency.

A spur-reduction technique for a 5-GHz frequency synthesizer

Abstract: A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-mum CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 mus