Showing papers on "Voltage regulator published in 2019"
TL;DR: The comparative results show that the combination of SC with AVR hardware-in-the-loop test and SI offers a better improvement not only on frequency stability but also on the system synchronism under various operating conditions.
Abstract: Inertia reduction due to high-level penetration of converter interfaced components may result in frequency stability issues This paper proposes and analyzes different strategies using synchronous condenser (SC), synthetic inertia (SI) of wind power plant, and their combination to enhance the frequency stability of low-inertia systems under various scenarios and wind conditions Furthermore, one of the SC models includes hardware of automatic voltage regulator (AVR) for better representation of the reality is implemented The simplified Western Danish power system simulated in real-time digital simulator is used as a test system of low inertia to demonstrate the effectiveness of the strategies The comparative results show that the combination of SC with AVR hardware-in-the-loop test and SI offers a better improvement not only on frequency stability (rate of change of frequency and frequency deviation) but also on the system synchronism under various operating conditions
128 citations
TL;DR: This paper focuses on the optimal network reconfiguration problem of distribution systems via an unbalanced ac optimal power flow framework, which rigorously addresses operation characters of unbalanced network, DERs, and voltage regulators (VRs).
Abstract: Network reconfiguration has long been used by distribution system operators to achieve certain operation objectives such as reducing system losses or regulating bus voltages. In emerging distribution systems with a proliferation of distributed energy resources (DERs), co-optimizing network topology and DERs’ dispatches could further enhance such operational benefits. This paper focuses on the optimal network reconfiguration problem of distribution systems via an unbalanced ac optimal power flow framework, which rigorously addresses operation characters of unbalanced network, DERs, and voltage regulators (VRs). Two VR models with continuous and discrete tap ratios are studied and compared. The proposed co-optimization problem is formulated as a mixed-integer chordal relaxation-based semidefinite programming model with binary variables indicating line-switching statuses and tap positions. Several acceleration strategies by studying the structure of distribution networks are explored for reducing the number of binary variables and enhancing the computational performance. Case studies on modified IEEE 34-bus and 392-bus systems illustrate the effectiveness of the proposed approach.
114 citations
TL;DR: The proposed algorithm adapts energy-optimized series voltage compensation, which results in a reduction of energy storage requirement and model-based computer simulation studies and real-time experimental results validate the effectiveness of the proposed control algorithm.
Abstract: This paper deals with the protection of critical loads from voltage-related power quality issues using a dynamic voltage restorer (DVR). A generalized control algorithm based on instantaneous space phasor and dual $P$ - $Q$ theory has been proposed to generate the instantaneous reference voltages to compensate the load voltages with direct power flow control. The proposed algorithm adapts energy-optimized series voltage compensation, which results in a reduction of energy storage requirement. The proposed DVR control scheme can support the load from voltage-related power quality issues irrespective of the load current profile. Each leg of the three-phase three-leg split capacitor inverter is used to inject series compensation voltage in respective phases of the system. Model-based computer simulation studies and real-time experimental results validate the effectiveness of the proposed control algorithm.
81 citations
TL;DR: A novel design method, sine-cosine algorithm (SCA) is presented in this paper to determine optimum proportional-integral-derivative (PID) controller parameters of an automatic voltage regulator (AVR) system and was found efficient and robust in improving the transient response of AVR system.
Abstract: A novel design method, sine-cosine algorithm (SCA) is presented in this paper to determine optimum proportional-integral-derivative (PID) controller parameters of an automatic voltage regulator (AV...
74 citations
TL;DR: The results indicate that the full-bridge series regulator can perform a true PPP, whereas the flyback series-regulator processes the same amount of power as that processed by conventional nonisolated boost converters and cannot be considered a partial-power topology.
Abstract: This paper proposes an analytical methodology to evaluate the power processed by dc–dc converters operating as series voltage regulators, which provide an alternative to increase efficiency in photovoltaic systems. Via the analysis of both active and nonactive power processing, the proposed methodology allows to clearly distinguish among circuit topologies as truly partial-power processing (PPP) or just partial active power processing topologies. When an isolated dc–dc topology is connected in series as a voltage regulator, the overall processed power can be reduced, which reduces power losses and improves efficiency. Conversely, this paper also demonstrates that some series-regulator topologies may not actually reduce the proportion of nonactive processed power. To demonstrate the applications of the proposed methodology and to emphasize its significance, two well-known series-connected voltage regulators (flyback and full-bridge phase shift) and a full-power regulator (boost) were evaluated. The results indicate that the full-bridge series regulator can perform a true PPP, whereas the flyback series-regulator processes the same amount of power as that processed by conventional nonisolated boost converters and cannot be considered a partial-power topology. This study finding contradicts assertions in the literature that this topology achieves high-efficiency dc–dc conversion through PPP. To confirm the theoretical analysis, experimental results from three 750-W prototypes are presented alongside its simulations.
62 citations
TL;DR: Effective computational strategies are proposed to allow the application of predictor-corrector primal-dual interior point method to solve optimization problems in real-time with a large number of constraints and variables, including discrete variables corresponding to switched capacitors and voltage regulators.
Abstract: Smart inverters provide additional control capability to help optimize the operation of distribution systems This paper proposes a framework for exact optimal active and reactive power dispatch of distributed photovoltaic (PV) generation, switched capacitors, and voltage regulators in large multi-phase unbalanced distribution systems The objectives of the optimal dispatch are minimization of the energy loss, PV active power curtailment, and operations of capacitors and voltage regulators, in addition to elimination of voltage violations and reverse power flow The optimization problem is formulated in rectangular coordinates as a nonlinear, nonconvex problem Effective computational strategies are proposed to allow the application of predictor-corrector primal-dual interior point method to solve optimization problems in real-time with a large number of constraints and variables, including discrete variables corresponding to switched capacitors and voltage regulators The accuracy of the numerical solution and the ability to implement the proposed framework are validated using the unbalanced multi-phase IEEE 34-bus and EPRI 2,998-bus distribution systems with 15-minute load and PV data The results show a significant loss reduction and elimination of both voltage violations and reverse power flow
60 citations
TL;DR: This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer.
Abstract: This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-flip-flop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast response, LP consumption, and excellent stability at the same time. In addition to that, the DLDO has a built-in active voltage positioning (AVP) for lower peak-to-peak voltage deviation during load step. The load capacitor is only 40 pF, and the total core area of the DLDO is 0.0374 mm2. A 50-mA step in load current produces a voltage droop of 108 mV, which is recovered in 1.24 $\mu \text{s}$ . It can operate for a wide input voltage from 0.6 to 1.2 V while generating a 0.4–1.1-V output for a maximum load current of 100 mA. The peak current efficiency is 99.5% and the figure of merit (FOM) is 1.38 ps.
54 citations
TL;DR: In this article, a self-driven photodetection system with a MoS2 nanosheets photoder as light intensity sensor, a vertical contact-separate mode triboelectric nanogenerator (CS-TENG) as power source, and several LEDs as alarm was proposed.
45 citations
TL;DR: This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB) that employs an energy-efficient, single-ended ground-referenced signaling scheme and employs a novel power supply regulation scheme at both ends.
Abstract: This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10−15. A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10−15. Overall link die area is 686 $\mu \text{m}\,\,\times $ 565 $\mu \text{m}$ with the transceiver circuitry taking up 20% of the area. The transceiver’s on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.
43 citations
TL;DR: This paper investigates a combined AGC and ED control methodology for a power system with CAs containing multiple hybrid energy resources that cannot be simply aggregated into a single equivalent source, and indicates that the proposed AGC optimal control strategy offers superior performance compared to traditional and recently published economic AGC strategies.
Abstract: New power system control methodologies have recently been proposed that combine economic dispatch (ED) and automatic generation control (AGC) in order to maintain economic operation when the generation mix incorporates a high penetration of renewable energy sources. The theoretical framework that underpins these techniques assumes that an aggregated control area (CA) model can be defined, assuming that the dynamic response of the entire CA is dominated by a single energy source, typically a steam-turbine generator. This paper investigates a combined AGC and ED control methodology for a power system with CAs containing multiple hybrid energy resources that cannot be simply aggregated into a single equivalent source. An optimization approach is then used to develop a control law and parameter design algorithm for each energy source, which accounts for their individual dynamics while aggregating the generators output to match with the target output of the CA. The performance of the proposed AGC and ED controller is demonstrated using simulation studies of an interconnected power system, conducted within the DIgSILENT power factory platform. This model incorporates non-linear network system dynamics and control loops within automatic voltage regulators and power system stabilizers. The study results indicate that the proposed AGC optimal control strategy offers superior performance compared to traditional and recently published economic AGC strategies, particularly when the generation mix includes both dispatchable conventional sources and a high penetration of non-dispatchable or semi-dispatchable sources such as wind.
39 citations
TL;DR: To overcome unbalanced conditions and to maintain voltage at PCC, a positive, negative and zero sequence-based current controller with reactive power compensation is proposed and found to be accurate.
Abstract: Distribution system possesses high resistance to reactance ratio and unbalanced load profile. Introduction of power electronic devices such as solar photovoltaic (PV) inverter in the distribution system leads to power imbalance and unregulated voltage profile at the point of common coupling (PCC) because these devices having low-voltage ride through feature remain connected to grid during fault and inject balanced current to unbalanced fault. Also, high PV integration may increase the voltage at PCC beyond its desired limit. To overcome such unbalanced conditions and to maintain voltage at PCC, a positive, negative and zero sequence-based current controller with reactive power compensation is proposed in this work. The sequence controller controls the sequence currents to their reference command. DC-link voltage regulator, reactive power compensator and PCC voltage regulator decide the references for sequence currents. The proposed reactive power compensator uses both positive sequence voltage at PCC and reactive power supplied by the filter capacitor to generate the reactive power reference value. Feedforward and feedback actions are involved in the controller to produce switching pulses for inverter. The proposed method is tested in OPAL-RT for real-time validation using IEEE 13 bus distribution system model and found to be accurate.
TL;DR: In this paper, the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced was analyzed, and an optimized design of the neutral inductors and filter inductors was proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors.
Abstract: The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α–β–0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter.
TL;DR: A fully distributed optimization method that combines the alternative direction multiplier method (ADMM) with the branch and bound method (BBM) for regional DNs to deal with the voltage violation problem caused by large-scale PV access is presented.
Abstract: With the increasing penetration of distributed photovoltaics (PVs), the operation and control of distribution networks (DNs), especially voltage control, have become more complicated. To deal with the voltage violation problem caused by large-scale PV access, this paper presents a fully distributed optimization method that combines the alternative direction multiplier method (ADMM) with the branch and bound method (BBM) for regional DNs. The total cost of active power losses and PV generation losses is minimized by making full use of the voltage regulation resources, e.g., reactive power compensators, step voltage regulators (SVR), and PV inverters, and the ADMM is employed to realize the intra-regional optimization and inter-regional coordination. To overcome the non-convex problem that is introduced by the SVR, the constraints of real-value tap positions are reformulated as linear inequality constraints of boundary voltages and added to the original problem, then the integer optimal solutions of SVR tap positions are obtained by BBM. The effectiveness of the proposed method is verified via numerical simulations on a practical 32-bus DN in China and a modified IEEE123-bus system.
TL;DR: This paper will examine full converter solutions which incorporate meaningful energy storage at a DC bus and reduced energy storage scenarios or storage free solutions such as matrix converter (MC) based devices.
Abstract: In the past five years substantial amounts of rooftop photovoltaic (PV) generation have been installed across the low voltage distribution networks. These networks often have design lifetimes of 40 years. Most of the existing distribution networks were constructed, and the voltage profiles set, prior to the rapid uptake of PV. When power quality difficulties arise reconstruction or some other form of intervention is required. This review will focus on power electronic options for voltage profile management in networks with high penetrations of PV. A voltage profile improvement can be achieved with a range of series or shunt connected devices. The traditional voltage regulator adds a series compensation voltage and electronic and electro-mechanical variations exist. Shunt devices attempt to influence voltage with reactive or real power flows when storage is allowed. A shunt device is additionally capable of phase balancing which may substantially raise the allowable PV fraction. In addition to the topological choices, the converter choice will impact upon capability. This paper will examine full converter solutions which incorporate meaningful energy storage at a DC bus and reduced energy storage scenarios or storage free solutions such as matrix converter (MC) based devices.
TL;DR: The simulation results on IEEE 33-bus distribution network with real-world data have validated the effectiveness of the proposed voltage regulation method and a decentralised voltage control is designed to regulate voltage ramp-rate for mitigating voltage fluctuations.
Abstract: In modern power distribution networks, voltage fluctuations and violations are becoming two major voltage quality issues due to high-level penetration of stochastic renewable energies (e.g. wind and solar power). In this study, a hybrid control strategy based on power inverters for voltage regulation in distribution networks is proposed. Firstly, a decentralised voltage control is designed to regulate voltage ramp-rate for mitigating voltage fluctuations. As a beneficial by-product, the var capacity from the inverters become smoothed. Then, a distributed voltage control is developed to fairly utilise the var capacity of each inverter to regulate the network voltage deviations. Furthermore, once there is a shortage of var capacity from inverters, on-load tap changers control will supplement to provide additional voltage regulation support. The simulation results on IEEE 33-bus distribution network with real-world data have validated the effectiveness of the proposed voltage regulation method.
TL;DR: A sliding mode (SM) decentralized excitation controller for multimachine power systems is designed to stabilize the speed and regulate the terminal voltage of each generator in the system using the passivity technique and a nonlinear observer is designed.
Abstract: In this brief, a sliding mode (SM) decentralized excitation controller for multimachine power systems is designed to stabilize the speed and regulate the terminal voltage of each generator in the system. To achieve the speed stabilization, a sliding manifold is designed using the passivity technique. An integral SM controller is proposed to reject internal and external perturbations, taking advantage of the energy properties of the power systems, in the SM motion on the designed manifold. Then, an SM voltage regulator is included in the control scheme, and a logic control is formulated to manage two proposed control laws for the speed and terminal voltage. Finally, to estimate the unmeasured rotor fluxes a nonlinear observer is designed. The proposed control scheme was tested through simulation on an equivalent of the Western System Coordinating Council under small and large perturbations.
22 Feb 2019
TL;DR: This paper demonstrates improved power and EM SCA resistance of standard (unprotected) 128b AES engines with parallel and serial datapaths via an on-die security-aware all-digital series low-dropout (DLDO) regulator, commonly used for fine-grain SoC power management.
Abstract: Side channel attacks (SCA) exploit data-dependent information leakage through power consumption and electromagnetic (EM) emissions from cryptographic engines to uncover secret keys. Integrated inductive voltage regulators (IVR) with a randomized control loop [1] or switching frequency [2], and random voltage dithering [3] have demonstrated improved power side-channel analysis (PSCA) resistance. Simulation studies have shown PSCA resistance via shunt linear regulators [4]. This paper demonstrates improved power and EM SCA resistance of standard (unprotected) 128b AES engines with parallel (P-AES, 128b) and serial (S-AES, 8b) datapaths via an on-die security-aware all-digital series low-dropout (DLDO) regulator, commonly used for fine-grain SoC power management. The security-aware DLDO improves SCA resistance using control-loop induced perturbations in a baseline DLDO, enhanced by a random switching noise injector (SNI) via power stage control and a randomized reference voltage (R-VREF) generator coupled with all-digital clock modulation (ADCM).
TL;DR: In this paper, an unbalanced backward-forward sweep load flow method is formulated to analyze the unbalanced operation of three-phase distribution systems. And the cat swarm optimiser is implemented to obtain the optimal planning of voltage regulating devices and dispatchable distributed generation units to achieve the lowest uncertainty influence on the voltage fluctuations.
Abstract: The penetration of renewable energy sources (RESs) in distribution systems faces many issues due to their output uncertainty resulted from climate conditions. The uncertainty impacts on the voltage fluctuations are reduced by using a proposed bi-stage method. At first, the system voltage is controlled by determining the optimal setting of voltage-regulating devices such as voltage regulators, transformer tap changers and static VAR compensator. Then, the dispatchable distributed generation (DDGs) units are accompanied by the voltage regulating devices to achieve more reduction in the voltage fluctuations. In this line, unbalanced backward–forward sweep load flow method is formulated to analyse the unbalanced operation of three-phase distribution systems. The main objectives of the proposed method are to reduce voltage fluctuations to maintain voltage profile within its permissible limits. In addition, the cat swarm optimiser (CSO) is implemented to obtain the optimal planning of voltage regulating devices and DDGs to achieve the lowest uncertainty influence on the voltage fluctuations. The proposed method is applied to a real unbalanced IEEE 34-bus distribution test system. The highest capability of CSO algorithm, i.e. CSO provides the highest reduction on the voltage fluctuations, is proven compared with particle swarm optimisation, harmony search and water cycle algorithms.
TL;DR: To the authors’ knowledge, this work is the first attempt to estimate such a full set of dynamic state variables and parameters, using just external measurements taken at the generator terminal bus.
TL;DR: In this article, the impact of wind energy on the small-signal stability of the power system is investigated and different combinations of AVR and PSS types are considered to mitigate the undesirable alterations.
Abstract: The increasing penetration of wind farms in the energy sector directly affects the dynamic behavior of the power system. The increasing use of wind energy in the power system worsens its stability and inherently influences the firmness of a small signal. To investigate these effects, one of the synchronous generators (SGs) of the grid is considered defective and is replaced by a doubly fed induction generator (DFIG)-based wind farm of the same rating. The small-signal stability of a power system is usually evaluated via eigenvalue analysis where local-area and inter-area oscillatory modes for the New England test system are identified. SG controls, such as automatic voltage regulator (AVR) and power system stabilizer (PSS), are added to attenuate the generated disturbances. In this study, the impact of wind energy on the small-signal stability of the power system is investigated. Different combinations of AVR and PSS types are considered to mitigate the undesirable alterations. A comparative study is performed based on numerical simulations to choose the best combination of AVR and PSS types. The obtained results prove that the proposed combination yields good results in terms of stability enhancement both under normal operating conditions and in DFIG-based wind farms.
03 Apr 2019
TL;DR: This work is to design a low-cost monitoring system for the maximum power point tracking (MPPT) in a PV system and a website has been designed to store and display the monitored data in real time.
Abstract: Integrating the Internet of Things (IoT) technology in solar photovoltaic (PV) systems is considered as an important aspect for monitoring, supervising and performances evaluation. The main aim of this work is to design a low-cost monitoring system for the maximum power point tracking (MPPT) in a PV system. Two electronics board have been developed: a data-acquisition sensing and a DC-DC boost converter. The designed monitoring board consists of an embedded board (Arduino Mega 2560 based upon ATmega2560), current and voltage sensors, voltage regulator Mini BEC, LCD Display, and a WiFi module ESP8266 to transmit the monitored data ( $I_{PV}, V_{PV}, V_{L}, I_{L}$ and $D$ ) on the internet. In addition, a website has been also designed to store and display the monitored data in real time. The designed prototype has been verified experimentally at Renewable Energy Laboratory (REL) of Jijel University, Algeria. Based on the monitored data the users can check easily if the system works well or not by just comparing the measured output power with the one expected by a model.
TL;DR: The results show the effectiveness of such a voltage regulator for the radial dc microgrid, especially under critical load condition.
Abstract: The concept of a novel series voltage regulator (SVR) for controlling the dc-bus voltage of a radial dc microgrid is presented in this paper. The proposed SVR uses a dual-active-bridge dc–dc converter followed by a full-bridge dc–dc converter. It injects dynamic voltage in series with the dc grid to compensate resistive drop over the network. As a result, the voltage level at the different points of the grid becomes independent of load variation and stays within the specified limit. Note that the required power rating of the SVR is very low (say 2.7%) compared to the load demand considering 5% voltage regulation. In this paper, the voltage regulator is connected at the midpoint of the grid, but it may be connected in some other locations to get optimal rating of the same. The proposed configuration is simulated in MATLAB/SIMULINK at a 380-V level to check the dynamic performance under various operating conditions. A scaled-down version (at 30-V level) of the proposed system is developed in the laboratory to experimentally validate the concept. The results show the effectiveness of such a voltage regulator for the radial dc microgrid, especially under critical load condition.
01 Sep 2019
TL;DR: A particle swarm optimization, fuzzy proportional integral derivative (PSOFPID) controller using MATLAB for a set point voltage and frequency to ease the frequency and the terminal potential difference constantly under any operating conditions and loads.
Abstract: The role of an intelligent control system with a certain stage of autonomy is prerequisite for effective operation. We designed a particle swarm optimization, fuzzy proportional integral derivative (PSOFPID) controller using MATLAB for a set point voltage and frequency. The projected controller intended to ease the frequency and the terminal potential difference constantly under any operating conditions and loads which can be attained in the wanted range via the rule of the generation system. PSOFPID used to carry out the AVR system auctions main voltage control. The existing algorithm was based on particle swarm optimization (PSO), and Sugeno fuzzy logic (SFL). It required optimal tuning for thematic factory operation of the generation system. The newly developed controller combined the PSO and fuzzy logic control (FLC) to determine the optimal PID controller of generator parameters in the AVR system. The PSOFPID controller was used as a hybrid full control system for the voltage and frequency. Optimal PID gains obtained by a combined PSO and SFL for various operating conditions of PSO (β and know about birds’ no.) were employed to develop the principle subject of the Sugeno fuzzy system. The hybrid controller arranged the control signal based on communication and thereby decreases the voltage error and the swaying in the terminal voltage and frequency control process. An outstanding potential and frequency control presentation was achieved when the projected hybrid controller was broken on the AVR system in synchronous generator to improve the transient response.
TL;DR: High efficiency is attained by the proposed converter due to extended duty cycle, low number of switches, and soft switching operation while the converter driver is just like the conventional buck converter.
Abstract: This paper proposes a high-step-down dc–dc converter with continuous output current which utilizes coupled-inductors. Another main feature of this converter is applying the same number of switches as the synchronous buck converter. The introduced converter is suitable for non-isolated low-voltage high-current applications, especially voltage regulator modules (VRMs) with 12-V-input. Owing to extension of the duty cycle, the main mosfet current stress and the synchronous rectifier switch voltage stress are significantly reduced. However, the discharge of the leakage inductance energy increases the main mosfet voltage stress. By employing a simple lossless clamp/snubber circuit the leakage inductance energy is recovered, the voltage spike across the main mosfet is clamped, and the turn- off switching losses are reduced. There is at least one inductor in all current paths which creates an intrinsic protection against current shoot-through and provides zero-current-switching (ZCS) turn- on for the main mosfet. High efficiency is attained by the proposed converter due to extended duty cycle, low number of switches, and soft switching operation while the converter driver is just like the conventional buck converter. Due to the single-phase structure of the proposed converter, this converter is a viable alternative to the buck VRM. Similar to the other converters using coupled-inductors, the complexity of coupled-inductors design and the space occupied by coupled-inductors can be considered as drawbacks. A prototype of the proposed converter is implemented to verify the converter operation and the theoretical analysis.
TL;DR: Simulation and experimental results confirm the expected performance of the proposed LQRI controller for insolation and load variations.
Abstract: This paper presents a multifunctional single-stage residential photovoltaic power supply based on a linear quadratic regulator (LQR). The system makes use of a single-phase power converter connected to the grid through an LCL filter. A robust LQR with added integral action (LQRI) controller is designed to incorporate added functions such as a power line conditioner, an active power regulator, and a voltage stabilizer. The perturb-and-observe algorithm is used to generate the reference signal for the fluctuating dc bus voltage as well as to extract the maximum power from the solar panels. Full modeling of the converter in the D–Q reference frame is presented. An LQRI is designed to achieve the optimal multifunctionality operation of the residential power supply. Simulation and experimental results confirm the expected performance of the proposed controller for insolation and load variations.
TL;DR: An online adaptive optimal controller is firstly designed to optimize the performance of an automatic voltage regulator (AVR), and an optimal quadratic tracking problem is defined based on the error between the synchronous generator’s terminal voltage and its desired value.
TL;DR: The results demonstrate that the proposed FHODFC provides less percentage overshoot, settling time, rise time, and peak time than other proposed controllers, i.e., HODFC.
Abstract: This paper proposes a high-order differential feedback controller (HODFC) and a fractional high-order differential feedback controller (FHODFC) to improve regulating ability of a commonly used automatic voltage regulator (AVR) system. In controller design process, particle swarm optimization (PSO) algorithm is utilized together with analytic approach. A constrained optimization problem is solved by PSO algorithm considering a specified objective function to obtain a less setting time, percentage overshoot, and regulation error. In order to test the performance of the proposed controllers, optimally tuned (proportional–integral–derivative) PID controllers available in the literature are implemented. The results demonstrate that the proposed FHODFC provides less percentage overshoot, settling time, rise time, and peak time than other proposed controllers, i.e., HODFC. Furthermore, the performance of the several available PID controllers is significantly worse than both of the proposed controllers in terms of transient response characteristics.
01 Jan 2019
TL;DR: In this article, a 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 μm2), whose location, size and shape are determined by design.
Abstract: Monolithic 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 μm2), whose location, size and shape are determined by design. Details of the improved location-controlled-grain (LCG) technique are presented. A voltage regulator implemented with the BEOL switch arrays using external control signals shows better theoretical figure of merit (FOM) of 0.089ns than 2D voltage regulators of 0.43ns.
01 Feb 2019
TL;DR: This paper presents an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents.
Abstract: Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 \mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $\lt/p\gt\lt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.