Showing papers by "Chenming Hu published in 2014"

Field-Effect Transistors Built from All Two-Dimensional Material Components

Abstract: We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including the semiconductor, insulator, and metal layers. Specifically, MoS2 is used as the active channel material, hexagonal-BN as the top-gate dielectric, and graphene as the source/drain and the top-gate contacts. This transistor exhibits n-type behavior with an ON/OFF current ratio of >106, and an electron mobility of ∼33 cm2/V·s. Uniquely, the mobility does not degrade at high gate voltages, presenting an important advantage over conventional Si transistors where enhanced surface roughness scattering severely reduces carrier mobilities at high gate-fields. A WSe2–MoS2 diode with graphene contacts is also demonstrated. The diode exhibits excellent rectification behavior and a low reverse bias current, suggesting high quality interfaces between the stacked layers. In this work, all interfaces are based on van der Waals bonding, presenting a unique device architecture where crystal...

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Abstract: BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Abstract: Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 °C. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.

Modeling of GaN-Based Normally-Off FinFET

Abstract: In this letter, a macromodel for normally-off (enhancement mode) AlGaN/GaN-based FinFET (2-DEG channel at top with two MOS like sidewall channels) is proposed. AlGaN/GaN-based FinFET devices have improved gate control on the channel due to additional sidewall gates compared with planar structures, but device characteristics exhibit strong nonlinear dependence on fin-width. The proposed model captures both 2-DEG and sidewall channel conduction as well as the fin-width dependency on device characteristics. Model shows excellent agreement with state-of-the-art experimental data.

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for V th matching and CMOS-compatible 3DFETs

Abstract: Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3–16 layers) of the transition-metal dichalcogenide (TMD), MoS 2 to Si fin and nanowire resulted in improved (+25%) I on,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.

Modeling 20-nm Germanium FinFET With the Industry Standard FinFET Model

Abstract: In this letter, we present modeling results for germanium p-type FinFETs using the industry standard Berkeley Spice Common Multi-gate Field Effect Transistor (BSIM-CMG) model. The effect of perpendicular electrical field on hole mobility in germanium FinFETs is found to be different from silicon FinFETs. We present an updated Ge mobility equation to account for this difference. With this single update, BSIM-CMG agrees very well with the measured I-V data of Ge FinFETs with a gate-length from 130 to 20 nm. We conclude that a production quality standard model is available for simulation of circuits employing p-type Ge FinFET.

Advanced metal and dielectric barrier cap films for Cu low k interconnects

Abstract: Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9–1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.

BSIM-IMG with improved surface potential calculation recipe

Abstract: In this paper, we have reported the improved surface potential calculation in the BSIM-IMG model for FDSOI MOSFETs. Model validation is done with the experimental data provided by Low-power Electronics Association and Project (LEAP). The model shows accurate behavior for C-V and I-V characteristics while keeping smooth behavior for their higher order derivatives. Model has smooth transition from weak inversion to strong inversion and satisfies DC and AC symmetry tests.

Body-bias effect in SOI FinFET for low-power applications: Gate length dependence

Abstract: We study the gate length dependence of body-bias effect in SOI FinFETs. Using measurements and simulations we show that body-bias effect is enhanced as the gate length is decreased. We study the impact of channel doping and device geometry on body-bias effect.

Interconnects exhibiting enhanced electromigration short-length effects by line width variation

Abstract: A novel model and approach for obtaining improved electromigration short-length effects are reported. The results for a structure with Dual Damascene copper-based metallization and two width regions demonstrate that increasing the line width for a portion of the line length generates longer electromigration lifetimes. Moreover, the lifetimes are accurately characterized by introducing an equivalent length for the structure that depends on the width and length of each region. The results are explained in terms of a modulation of the stress profile in the structure with more than one width region. A consequence of these findings is increased design flexibility since more options are available to improve the electromigration reliability of short interconnects.

Series resistance and mobility in mechanically-exfoliated layered transition metal dichalcogenide MOSFETs

Abstract: We show that transmission line method, where a set of devices are used, does not always correctly estimate series resistance of mechanically-exfoliated transition metal dichalcogenide MOSFETs. We calculate series resistance and carrier mobility from current-voltage characteristics of a single device. We show that series resistance should be considered for accurate mobility calculation even for long channel devices.

Impact of channel doping on the device and NBTI performance in FinFETs for low power applications

Abstract: We present device-level characterization of digital, analog and NBTI parameters for p-FinFETs with different channel doping. We show that using channel doping we can trade-off device and NBTI performance. In p-FinFETs, Arsenic doped channel has better digital and analog performance and Boron doped channel has superior NBTI performance. Forward body bias reduces NBTI degradation in p-FinFETs.