Journal ArticleDOI
Modeling 20-nm Germanium FinFET With the Industry Standard FinFET Model
Reads0
Chats0
TLDR
In this article, the effect of the perpendicular electrical field on hole mobility in germanium FinFETs is investigated and an updated Ge mobility equation is presented to account for this difference.Abstract:
In this letter, we present modeling results for germanium p-type FinFETs using the industry standard Berkeley Spice Common Multi-gate Field Effect Transistor (BSIM-CMG) model. The effect of perpendicular electrical field on hole mobility in germanium FinFETs is found to be different from silicon FinFETs. We present an updated Ge mobility equation to account for this difference. With this single update, BSIM-CMG agrees very well with the measured I-V data of Ge FinFETs with a gate-length from 130 to 20 nm. We conclude that a production quality standard model is available for simulation of circuits employing p-type Ge FinFET.read more
Citations
More filters
Journal ArticleDOI
Hexagonal germanium formation at room temperature using controlled penetration depth nano-indentation
TL;DR: The inelastic deformation mechanism is found to depend critically on the indentation penetration depth and can be reliably used to induce phase transformation in Ge-on-Si with technological interest as a narrow band gap material for mid-wavelength infrared detection.
Journal ArticleDOI
Capacitance Modeling in III–V FinFETs
Chandan Yadav,Juan Pablo Duarte,Sourabh Khandelwal,Amit Agarwal,Chenming Hu,Yogesh Singh Chauhan +5 more
TL;DR: In this paper, a physics-based model of charge density and capacitance for III-V channel double-gate nMOSFETs is presented, which accurately accounts for the impact of quantum capacitance on gate capacitance with applied gate voltage.
Journal ArticleDOI
Compact Model for Geometry Dependent Mobility in Nanosheet FETs
Avirup Dasgupta,Shivendra Singh Parihar,Harshit Agarwal,Pragya Kushwaha,Yogesh Singh Chauhan,Chenming Hu +5 more
TL;DR: In this article, an updated compact model for mobility in Nanosheet FETs is proposed, which takes all of the effects of nanosheet scaling into account and is implemented in Verilog-A and validated with experimental data.
Journal ArticleDOI
Modeling of nonlinear thermal resistance in FinFETs
Bala Krishna Kompala,Pragya Kushwaha,Harshit Agarwal,Sourabh Khandelwal,Juan Pablo Duarte,Chenming Hu,Yogesh Singh Chauhan +6 more
TL;DR: In this paper, the authors investigated the thermal resistance of FinFETs with the variation in the number of fin, shape of fin and fin pitch, and proposed a model for thermal resistance behavior correctly with N fin and F pitch variation.
Journal ArticleDOI
Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs
Mohit D. Ganeriwala,Chandan Yadav,Nihar R. Mohapatra,Sourabh Khandelwal,Chenming Hu,Yogesh Singh Chauhan +5 more
TL;DR: A compact model for semiconductor charge and quantum capacitance in III-V channel FETs is presented and is completely explicit and computationally efficient which makes it highly suitable for SPICE implementation.
References
More filters
Journal ArticleDOI
High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation
TL;DR: In this article, an ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al 2O3 layer between Hf2 and Ge, resulting in a low interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface.
Proceedings ArticleDOI
Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications
Marko Radosavljevic,G. Dewey,J. M. Fastenau,Jack Portland Kavalieros,Roza Kotlyar,Benjamin Chu-Kung,W. K. Liu,D. Lubyshev,Matthew V. Metz,K. Millard,Niloy Mukherjee,L. Pan,R. Pillarisetty,W. Rachmady,Uday Shah,Robert S. Chau +15 more
TL;DR: In this paper, a non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate to drain and gate-to-source separations (L SIDE) of 5nm are reported for the first time.
Journal ArticleDOI
Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages
TL;DR: In this paper, the universal dependence of N- and P-MOSFETs carrier mobility on effective vertical field E eff = (ηQ inv + Q b ) ϵ Si has been re-examined.
Journal ArticleDOI
Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping
Mark J. H. van Dal,Georgios Vellianitis,Blandine Duriez,Gerben Doornbos,C. H. Hsieh,Bi-Hui Lee,Kai-Min Yin,Matthias Passlack,Carlos H. Diaz +8 more
TL;DR: In this article, scaled Ge p-channel FinFETs fabricated on a 300mm Si wafer using the aspect-ratio-trapping technique were reported. But, the performance of the Ge pFET was limited by the fact that the trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current.
Journal ArticleDOI
Physical understanding of low-field carrier mobility in silicon MOSFET inversion layer
TL;DR: In this article, the gate field dependencies of the low-field mobilities of electrons and holes were studied and it was shown that by changing surface orientations and oxidation conditions the two-dimensional electron gas formulation can successfully explain eta = 1/3 (where eta is the weighting factor of mobile charge density used in calculating the effective field for the universal mobility curve).