Showing papers by "Pragya Kushwaha published in 2016"

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

Abstract: In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.

Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport

Abstract: In this letter, we present a unified compact model, which accurately captures carrier transport from the drift-diffusion to ballistic regime. This is a single unified model, which accounts for carrier degeneracy effects in ballistic transport. The model is implemented into the industry standard compact models for FinFETs, fully depleted silicon-on-insulator (FDSOI) devices and bulk MOSFETs: 1) Berkeley Spice model for common multi-gate; 2) Berkeley Spice model for independent multi-gate; and 3) BSIM6. The model is validated with experimental data and TCAD simulations for FDSOI devices, FinFETs, and bulk MOSFETs.

Modeling of nonlinear thermal resistance in FinFETs

Abstract: In this paper, self-consistent three-dimensional (3D) device simulations for exact analysis of thermal transport in FinFETs are performed. We analyze the temperature rise in FinFET devices with the variation in the number of fins (N fin), shape of fins and fin pitch (F pitch). We investigate that the thermal resistance R th has nonlinear dependency on N fin and F pitch. We formulate a model for thermal resistance behavior correctly with N fin and F pitch variation. The proposed formulation is implemented in industry standard Berkeley short-channel independent gate FET model for common multi-gate transistors (BSIM-CMG) and validated with both experimental data and TCAD simulations.

Characterization of RF Noise in UTBB FD-SOI MOSFET

Abstract: In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs

Abstract: In this paper, flicker noise behavior of lateral non-uniformly doped MOSFET is studied using impedance field method. Our study shows that Klaassen Prins (KP) method, which forms the basis of noise model in MOSFETs, underestimates flicker noise in such devices. The same KP method overestimates thermal noise by 2–3 orders of magnitude in similar devices as demonstrated in Roy et al. (2007). This apparent discrepancy between thermal and flicker noise behavior lies in origin of these noises, which leads to opposite trend of local noise power spectral density vs doping. We have modeled the physics behind such behavior, which also explain the trends observed in the measurements (Agarwal et al., 2015).

Predictive effective mobility model for FDSOI transistors using technology parameters

Abstract: by Pragya Kushwaha, Harshit Agarwal, Mandar Bhoir, Nihar R. Mohapatra, Sourabh Khandelwal, Juan Pablo Duarte, Yen-Kai Lin, Huan-Lin Chang, Chenming hu and Yogesh Singh Chauhan

Modeling of threshold voltage for operating point using industry standard BSIM-IMG model

Abstract: Threshold voltage is an important device parameter for MOSFET modeling as circuit designer needs to know the threshold voltage to bias the transistor in the required region of operation. In this paper, we have proposed an approach to calculate the threshold voltage for operating point information in the BSIM-IMG model which is the latest industry standard compact model for FDSOI transistors. The BSIM-IMG is the surface potential based model, and therefore threshold voltage is not explicitly available. The proposed model takes care of back-bias and other real device effects (CLM, DIBL etc) accurately. The model is developed to fulfill the demand of semiconductor companies for their commercial SPICE simulators and PDKs. We have shown model comparison with various popular threshold voltage extraction techniques. The model shows very good agreement with the measured data over wide range of device geometries, drain and body biases.

Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model

Abstract: Recently, experimental Germanium CMOS devices and circuit are reported for advanced technology nodes for the first time. In this paper, we have modeled Germanium On Insulator (GeOI) device with industry standard compact model for independent double gate MOSFET (BSIM-IMG) with updated mobility model. It is shown that BSIM-IMG with updated mobility model accurately captures static characteristics for both n-channel and p-channel devices, and reproduces experimental CMOS inverter characteristics. This is the first time, when a compact model is validated on experimental CMOS circuit operation of GeOI.

Modeling independent multi-gate MOSFETs

Abstract: This work presents the industry standard compact BSIM-IMG, a fully-featured turn-key compact model for independent multi-gate MOSFETs. The two independent (frontand back-gate) control of the channel charge in these devices enables novel applications wherein back-gate can be in depletion or inversion, and BSIM-IMG accurately models these scenarios. Modeling of the channel-charge in this device requires a consistent solution of coupled Poisson’s equations at the frontand the back-gate. This papers presents an analytical solution which is numerically robust and passes important quality tests for an industry grade compact model. To represent real device effects, several extra models are incorporated such as drain-induced barrier lowering, velocity saturation, short-channel effects, self-heating effect, mobility-field dependence, substrate-depletion effect, etc.

Impact of back plane doping on RF performance of FD-SOI transistor

Abstract: In this paper, we presents the effect of higher back plane doping on analog figure of merit of fully depleted-silicon on insulator (FD-SOI) MOSFETs at RF frequencies. Procedure for DC and RF parameter extraction at RF frequencies has been discussed. Surface potential based Industry standard BSIM-IMG model for FD-SOI MOSFETs with enhanced gate parasitic network is used for validation of extracted DC and RF parameters such as gate resistance, gate parasitic capacitance, output conductance, transconductance.