R
R. James
Researcher at Intel
Publications - 4
Citations - 1865
R. James is an academic researcher from Intel. The author has contributed to research in topics: NMOS logic & PMOS logic. The author has an hindex of 4, co-authored 4 publications receiving 1732 citations.
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Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Proceedings ArticleDOI
A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size
Sanjay Natarajan,M. Agostinelli,S. Akbar,M. Bost,A. Bowonder,V. Chikarmane,S. Chouksey,A. Dasgupta,K. Fischer,Q. Fu,Tahir Ghani,M. Giles,S. Govindaraju,R. Grover,W. Han,D. Hanken,E. Haralson,M. Haran,M. Heckscher,R. Heussner,Pulkit Jain,R. James,R. Jhaveri,I. Jin,Hei Kam,Eric Karl,C. Kenyon,Mark Y. Liu,Y. Luo,R. Mehandru,S. Morarka,L. Neiberg,Paul A. Packan,A. Paliwal,C. Parker,P. Patel,R. Patel,C. Pelto,L. Pipes,P. Plekhanov,M. Prince,S. Rajamani,J. Sandford,Sell Bernhard,Swaminathan Sivakumar,Pete Smith,B. Song,K. Tone,T. Troeger,J. Wiedemer,M. Yang,Kevin Zhang +51 more
TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
Proceedings ArticleDOI
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai,C. Auth,Sridhar Balakrishnan,M. Bost,Ruth A. Brain,V. Chikarmane,R. Heussner,Makarem A. Hussein,Jack Hwang,D. Ingerly,R. James,J. Jeong,C. Kenyon,E. Lee,Seung Hwan Lee,Nick Lindert,Mark Y. Liu,Z. Ma,T. Marieb,Anand Portland Murthy,Ramune Nagisetty,Sanjay Natarajan,J. Neirynck,Andrew Ott,C. Parker,J. Sebastian,R. Shaheed,Swaminathan Sivakumar,Joseph M. Steigerwald,S. Tyagi,Cory E. Weber,Bruce Woolery,Yeoh Andrew W,Kevin Zhang,M. Bohr +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Proceedings ArticleDOI
An advanced low power, high performance, strained channel 65nm technology
S. Tyagi,C. Auth,P. Bai,G. Curello,H. Deshpande,S. Gannavaram,Oleg Golonzka,R. Heussner,R. James,C. Kenyon,Seok-Hee Lee,Nick Lindert,Mark Y. Liu,Ramune Nagisetty,Sanjay Natarajan,C. Parker,J. Sebastian,Sell Bernhard,Swaminathan Sivakumar,A. St. Amour,K. Tone +20 more
TL;DR: In this article, an advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented at 1V and off current of 100nA/mum.