R
Ramune Nagisetty
Researcher at Intel
Publications - Â 27
Citations - Â 1528
Ramune Nagisetty is an academic researcher from Intel. The author has contributed to research in topics: PMOS logic & NMOS logic. The author has an hindex of 14, co-authored 27 publications receiving 1412 citations. Previous affiliations of Ramune Nagisetty include University of California, Berkeley.
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Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Proceedings ArticleDOI
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai,C. Auth,Sridhar Balakrishnan,M. Bost,Ruth A. Brain,V. Chikarmane,R. Heussner,Makarem A. Hussein,Jack Hwang,D. Ingerly,R. James,J. Jeong,C. Kenyon,E. Lee,Seung Hwan Lee,Nick Lindert,Mark Y. Liu,Z. Ma,T. Marieb,Anand Portland Murthy,Ramune Nagisetty,Sanjay Natarajan,J. Neirynck,Andrew Ott,C. Parker,J. Sebastian,R. Shaheed,Swaminathan Sivakumar,Joseph M. Steigerwald,S. Tyagi,Cory E. Weber,Bruce Woolery,Yeoh Andrew W,Kevin Zhang,M. Bohr +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Proceedings ArticleDOI
100 nm gate length high performance/low power CMOS transistor structure
Tahir Ghani,S. Ahmed,P. Aminzadeh,J. Bielefeld,P. Charvat,C. Chu,Michael K. Harper,P. Jacob,Chia-Hong Jan,Jack Portland Kavalieros,C. Kenyon,Ramune Nagisetty,Paul A. Packan,J. Sebastian,M. Taylor,J. Tsai,S. Tyagi,Simon Yang,M. Bohr +18 more
TL;DR: In this paper, the authors report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V and 3 nA/m I/sub OFF.
Proceedings ArticleDOI
An advanced low power, high performance, strained channel 65nm technology
S. Tyagi,C. Auth,P. Bai,G. Curello,H. Deshpande,S. Gannavaram,Oleg Golonzka,R. Heussner,R. James,C. Kenyon,Seok-Hee Lee,Nick Lindert,Mark Y. Liu,Ramune Nagisetty,Sanjay Natarajan,C. Parker,J. Sebastian,Sell Bernhard,Swaminathan Sivakumar,A. St. Amour,K. Tone +20 more
TL;DR: In this article, an advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented at 1V and off current of 100nA/mum.
Journal ArticleDOI
Organic Multi-Channel Optoelectronic Sensors for Wearable Health Monitoring
TL;DR: A systematic study of the reflectance oximeter sensor design in terms of component geometry, light emitter and detector spacing, and the use of an optical barrier between the emitters and detector to maximize sensor performance is reported.