Journal ArticleDOI
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity
Balaji Jayaraman,Derek H. Leu,Janakiraman Viraraghavan,Alberto Cestero,Ming Yin,John Golz,Rajesh R. Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian S. Iyer +12 more
TLDR
The design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity is described and high-temperature stress results show a projected data retention of 10 years at 125 °C.Abstract:
This paper describes the design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity. Charge trap transistors (CTTs) that exploit charge trapping and de-trapping behavior in high-K dielectric of 32-/22-nm Logic FETs are used as storage elements with logic-compatible programming voltages. A high-gain slew-sense amplifier (SA) is used to efficiently detect the threshold voltage difference ( $\Delta V_{\textrm {DIF}}$ ) between the true and complement FETs in the twin cell. Design-assist techniques including multi-step programming with over-write protection and block write algorithm are used to enhance the programming efficiency without causing a dielectric breakdown. High-temperature stress results show a projected data retention of 10 years at 125 °C with a signal loss of <30% that is margined in while programming, by employing a sense margining logic in the SA. Scalability of CTT has been established by the first demonstration of CTT-based MTPM in 14-nm bulk FinFET technology with read cycle time of 40 ns at 0.7-V VDD.read more
Citations
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Journal ArticleDOI
Total Ionizing Dose Responses of 22-nm FDSOI and 14-nm Bulk FinFET Charge-Trap Transistors
Rachel M. Brewer,En Xia Zhang,Mariia Gorchichko,Peng Fei Wang,Jonathan Cox,Steven Moran,Dennis R. Ball,Brian D. Sierawski,Daniel M. Fleetwood,Ronald D. Schrimpf,Subramanian S. Iyer,Michael L. Alles +11 more
TL;DR: In this paper, total ionizing-dose (TID) effects for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors were investigated.
Journal ArticleDOI
Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights
TL;DR: A fully CMOS-compatible multi-level non-volatile memory technology, especially suitable for storing the weights of artificial neural networks on chip with low cost, high density, and high power-efficiency is presented.
Journal ArticleDOI
14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing
Eric D. Hunt-Schroeder,Darren L. Anand,John A. Fifield,Michael Roberge,Dale Pontius,Mark Jacunski,Kevin Batson,Matthew Deming,Faraz Khan,Dan Moy,Alberto Cestero,Robert Katz,Z. Chbili,Edmund Banghart,L. Jiang,Balaji Jayaraman,Rajesh R. Tummuru,Ramesh Raghavan,Amit Mishra,Norman Robson,Toshiaki Kirihata +20 more
TL;DR: Hardware qualification certifies the OTPM to a 10-year 105 °C data retention specification and <3 PPM end of life bit error rate pre-ECC.
Journal ArticleDOI
CTT-Based Scalable Neuromorphic Architecture
TL;DR: In this paper , a novel spiking neuromorphic architecture is presented based on charge-trap transistors (CTTs) which are experimentally verified compute-in-memory devices.
Proceedings ArticleDOI
Design of a Delta Threshold Voltage Difference based fully Embedded Read Only Memory along with a Skew Sense Amplifier
TL;DR: A fast, on-chip solution is proposed in this technical paper wherein logic transistors are used to design a read only memory with completely zero added process complexity.
References
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Proceedings ArticleDOI
A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates
Sufi Zafar,Young-Hee Kim,Vijay Narayanan,Cyril Cabral,Vamsi Paruchuri,Bruce B. Doris,James H. Stathis,Alessandro C. Callegari,Michael P. Chudzik +8 more
TL;DR: In this paper, the authors present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials, including SiO 2/NiSi and SiO2/HfO2 devices with TiN and Re as gates.
Proceedings ArticleDOI
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
Norman Robson,John M. Safran,Chandrasekharan Kothandaraman,Alberto Cestero,Xiang Chen,R. Rajeevakumar,Alan J. Leslie,Dan Moy,T. Kirihata,Subramanian S. Iyer +9 more
TL;DR: The evolution and applications of electrical fuse solutions for 180 nm to 45 nm technologies at IBM are reviewed, and some insight into future uses in 32 nm technology and beyond with the eFUSE as a building block for the autonomic chip of the future is provided.
Journal ArticleDOI
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
Hidehiro Shiga,Daisaburo Takashima,Shinichiro Shiratake,Katsuhiko Hoya,Tadashi Miyakawa,Ryu Ogiwara,Ryo Fukuda,Ryosuke Takizawa,Kosuke Hatsuda,Fumiyoshi Matsuoka,Yasushi Nagadomi,Daisuke Hashimoto,Hisaaki Nishimura,Takeshi Hioka,Sumiko Doumae,Shoichi Shimizu,Mitsumo Kawano,Toyoki Taguchi,Yohji Watanabe,Shuso Fujii,Tohru Ozaki,Hiroyuki Kanaya,Yoshinori Kumura,Yoshiro Shimojo,Yuki Yamada,Yoshihiro Minami,Susumu Shuto,Koji Yamakawa,Souichi Yamazaki,Iwao Kunishima,Takeshi Hamamoto,Akihiro Nitayama,Tohru Furuyama +32 more
TL;DR: Three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF, and a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ¿m2.
Journal ArticleDOI
A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate
Woopyo Jeong,Jae-Woo Im,Doohyun Kim,Sang-Wan Nam,Dongkyo Shim,Myung-Hoon Choi,Hyun-Jun Yoon,Dae-Han Kim,You-Se Kim,HyunWook Park,Donghun Kwak,Sang-Won Park,Seok-Min Yoon,Wook-Ghee Hahn,Jinho Ryu,Sang-Won Shim,Kyung-Tae Kang,Jeong-Don Ihm,In-Mo Kim,Doo-Sub Lee,Ji-Ho Cho,Moosung Kim,Jae-Hoon Jang,Sang-Won Hwang,Dae-Seok Byeon,Hyang-ja Yang,Kitae Park,Kye-Hyun Kyung,Jeong-Hyuk Choi +28 more
TL;DR: The result of long and focused research in 3D stacking technology is developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest128 Gb NAND Flash.
Proceedings ArticleDOI
11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory
Chulbum Kim,Ji-Ho Cho,Woopyo Jeong,Park Il-Han,HyunWook Park,Doohyun Kim,Dae-Woon Kang,Sung-Hoon Lee,Ji-Sang Lee,Won-Tae Kim,Park Jiyoon,Yang-Lo Ahn,Ji-Young Lee,Jong-Hoon Lee,Seung-Bum Kim,Hyun-Jun Yoon,Jaedoeg Yu,Nayoung Choi,Yelim Kwon,Nahyun Kim,Hwajun Jang,Jonghoon Park,Seung-Hwan Song,Yong-Ha Park,Jinbae Bang,Sangki Hong,Byung-Hoon Jeong,Hyun-Jin Kim,Chunan Lee,Young-Sun Min,Inryul Lee,In-Mo Kim,Sung-Hoon Kim,Dongkyu Yoon,Ki-Sung Kim,Young-don Choi,Moosung Kim,Hyung-Gon Kim,Pansuk Kwak,Jeong-Don Ihm,Dae-Seok Byeon,Jin-Yub Lee,Kitae Park,Kye-Hyun Kyung +43 more
TL;DR: This work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction for 3D NAND array density scaling issues.