Journal ArticleDOI
A silicon‐based dual‐material double‐gate tunnel field‐effect transistor with optimized performance
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This article is published in International Journal of Numerical Modelling-electronic Networks Devices and Fields.The article was published on 2017-11-01. It has received 13 citations till now. The article focuses on the topics: Silicon bandgap temperature sensor & Tunnel field-effect transistor.read more
Citations
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Journal ArticleDOI
Hetero-gate-Dielectric Symmetric U-shaped gate tunnel FET
TL;DR: Heterogeneous gate dielectric is used in a nanoscale symmetric U-shaped gate tunnel FET (SUTFET), which resulted in ION, IOFF, subthreshold swing (SS), and Iambipolar enhancement as mentioned in this paper.
Journal ArticleDOI
A novel analytical approach to optimize the work functions of dual-material double-gate Tunneling-FETs
TL;DR: In this paper, the work function of a dual-material double-gate tunnel field effect transistor was optimized using analytical models, where the optimal value of work function for the material of the gate closer to the source was formulated in terms of device physical parameters including the work functions of the other material.
Proceedings ArticleDOI
Application of nanocavity embedded dual metal double gate TFET in biomolecule detection
TL;DR: In this paper, the authors analyzed the performance of nanocavity embedded dual metal double gate tunnel FET device as a label free biosensor for neutral biomolecule detection and found that the dual metal structure provides better sensitivity than the single metal counterpart.
Journal ArticleDOI
Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study
Journal ArticleDOI
An Analytical Modeling and Simulation of Surrounding Gate TFET with an Impact of Dual Material Gate and Stacked Oxide for Low Power Applications
TL;DR: In this article, an analytical model for modified Surrounding Gate Tunnel FET with gate stack engineering and different gate metals has been developed, considering the scaling advantageous of gate stack and high degree performance of dual material engineering.
References
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Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Related Papers (5)
Improvement of Subthreshold Characteristics of Dopingless Tunnel FET Using Hetero Gate Dielectric Material: Analytical Modeling and Simulation
G. Lakshmi Priya,Balamurugan N B +1 more
A Pseudo-2-D-Analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET
Rajat Vishnoi,M. Jagadesh Kumar +1 more