Journal ArticleDOI
A Traveling-Wave CMOS SPDT Using Slow-Wave Transmission Lines for Millimeter-Wave Application
TLDR
In this paper, a traveling-wave single-pole double-throw (SPDT) switch using slow-wave coplanar waveguides is implemented in a 65-nm triple-well CMOS process.Abstract:
In this letter, a traveling-wave single-pole double-throw (SPDT) switch using slow-wave coplanar waveguides is implemented in a 65-nm triple-well CMOS process. For performance improvement, double-well body-floating technique is used. The p-well layer and deep n-well layer of nMOSFET being, respectively, biased to -1.4 and 2.0 V, the measured SPDT exhibits an insertion loss of 2.8 dB and an isolation of 20 dB at 60 GHz. A measured input 1-dB compression point (ICP1dB) of 17 dBm is obtained at 35 GHz (16.3 dBm at 60 GHz by simulation). The total chip size is only 0.42 mm2 (780 μm× 540 μm) including all testing pads.read more
Citations
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Journal ArticleDOI
A Low-Loss and High Isolation D-Band SPDT Switch Utilizing Deep-Saturated SiGe HBTs
A. Cagri Ulusoy,Peter Song,Robert L. Schmid,Wasif Tanveer Khan,Mehmet Kaynak,Bernd Tillack,John Papapolymerou,John D. Cressler +7 more
TL;DR: In this paper, a single-pole double-throw switch, utilizing double-shunt, deep-saturated HBTs, is implemented in a 0.13$ SiGe BiCMOS technology, occupying 0.36$ of IC area.
Journal ArticleDOI
Miniaturized, Ultra-Wideband and High Isolation Single Pole Double Throw Switch by Using π-Type Topology in GaAs pHEMT Technology
TL;DR: An ultra-wideband high isolation behavior and the reduced dimension is achieved simultaneously with the proposed SPDT switch and the equivalent circuit model is built to interpret the mechanism of the improved technique.
Journal ArticleDOI
Compact Millimeter-Wave SPDT Switches and Wilkinson Power Combiners Implemented by LC-Based Spiral Transmission Lines
Xiangyu Meng,C. Patrick Yue +1 more
TL;DR: In this paper, the authors proposed an LC-based spiral transmission line structure, which can effectively reduce the area of ON-chip transmission lines, and implemented a 28 GHz single-pole double-throw (SPDT) switch and a 37 GHz Wilkinson power combiner with an area of only 0.028 mm2 in 65-nm CMOS.
Journal ArticleDOI
Source engineered tunnel FET for enhanced device electrostatics with trap charges reliability
TL;DR: In this article, a new configuration of tunnel field effect transistor (TFET) was proposed for improving current drivability of device along with reduced threshold voltage and improved high frequency response.
Journal ArticleDOI
A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch
TL;DR: In this paper, a loss compensation scheme for series-shunt single-pole double-throw (SPDT) switches operating in the 60 GHz band was proposed, which reduced the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch.
References
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Journal ArticleDOI
A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link
TL;DR: A directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies that requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption.
Journal ArticleDOI
CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency
Qiang Li,Yue Ping Zhang +1 more
TL;DR: The analysis shows that a series-only architecture using the customized transistor layout achieves better insertion loss and reasonable isolation, and a double-well body-floating technique is proposed and its effects are discussed.
Journal ArticleDOI
High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters
TL;DR: In this paper, the authors presented optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines), which were used to realize a 60 GHz bandpass filter, with T-junctions and open stubs.
Journal ArticleDOI
A 50 to 94-GHz CMOS SPDT Switch Using Traveling-Wave Concept
TL;DR: A fully integrated single-pole-double-throw transmit/receive switch has been designed and fabricated in standard bulk 90-nm complementary metaloxide semiconductor (CMOS) technology.
Journal ArticleDOI
Ultra Low-Loss 50-70 GHz SPDT Switch in 90 nm CMOS
Mehmet Uzunkol,Gabriel M. Rebeiz +1 more
TL;DR: This paper presents an ultra-low-loss 50-70 GHz single-pole double-throw (SPDT) switch built using a standard 90 nm CMOS process and is the lowest insertion loss 60 GHz SPDT in any CMOS technology.