Journal ArticleDOI
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options
TLDR
It is demonstrated how device subthreshold leakage current and subth threshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering.About:
This article is published in Microelectronics Journal.The article was published on 2011-05-01. It has received 27 citations till now. The article focuses on the topics: Subthreshold slope & Subthreshold conduction.read more
Citations
More filters
Journal ArticleDOI
Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region
TL;DR: A very good agreement of analytically modeled results with the TCAD simulated results for the three-terminal (3T) and four-Terminal (4T) Si-nTFET device was found.
Journal ArticleDOI
Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation
TL;DR: In this paper, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET for operation in the sub-threshold condition is proposed.
Journal ArticleDOI
An analytical modeling of charge plasma based Tunnel Field Effect Transistor with impacts of gate underlap region
Girish Wadhwa,Balwinder Raj +1 more
TL;DR: In this article, a compact model of source depletion, drain depletion and channel potential in the charge plasma based tunnel field effect transistor (U-CPBTFET) with two underlap regions (source-gate and gate-drain) is proposed and developed.
Journal ArticleDOI
Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap
TL;DR: In this paper, a compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance.
Journal ArticleDOI
Implementation of linearly modulated work function A σ B 1-σ gate electrode and Si 0.55 Ge 0.45 N+ pocket doping for performance improvement in gate stack vertical-TFET
Girish Wadhwa,Jeetendra Singh +1 more
TL;DR: In this paper, the characteristics of linearly graded work function (LGW) by utilizing the composition of binary metal alloy AσB1−σ gate electrode and Si-Si0.55Ge0.45 middle N+ pocket heterojunction at the interface of source and channel is explored in the high-k gate stack vertical-TFET (GS-VTFET).
References
More filters
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
Scaling theory for double-gate SOI MOSFET's
TL;DR: In this paper, a scaling theory for double-gate SOI MOSFETs is presented, which gives guidance for device design that maintains a sub-threshold factor for a given gate length.
Journal ArticleDOI
A continuous, analytic drain-current model for DG MOSFETs
TL;DR: In this article, a continuous analytic currentvoltage model for double-gate MOSFETs is presented, which is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation.
Related Papers (5)
Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors
Aditya Bansal,Kaushik Roy +1 more
Double gate-MOSFET subthreshold circuit for ultralow power applications
Jae-Joon Kim,Kaushik Roy +1 more