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High-Mobility GaSb Nanostructures Cointegrated with InAs on Si

TLDR
A process that enables cointegration of GaSb and InAs nanostructures in close vicinity on Si, a preferred material combination ideally suited for high-performance complementary III-V metal-oxide-semiconductor technology.
Abstract
GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors and mid-IR photodetectors. Here, we investigate the metalorganic chemical vapor deposition and properties of GaSb nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted selective epitaxy. A high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Detailed investigation of growth parameters reveals that the GaSb growth rate is governed by the desorption processes of an Sb surface layer and, in turn, is insensitive to changes in material transport efficiency. The GaSb crystal structure is typically zinc-blende with a low density of rotational twin defects, and even occasional twin-free structures are observed. Hall/van der Pauw measurements are conducted on 20 nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm2/(V s), which matches literature values for high-quality bulk GaSb crystals. Finally, we demonstra...

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High-Mobility GaSb Nanostructures Cointegrated
with InAs on Si
Mattias Borg
1,
, Heinz Schmid
1,*
, Johannes Gooth
1
, Marta D. Rossell
1,2
, Davide Cutaia
1
, Moritz
Knoedler
1
, Nicolas Bologna
1,2
, Stephan Wirths
1
, Kirsten E. Moselund
1
, Heike Riel
1
1.
IBM Research Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
2.
Electron Microscopy Center, EMPA, Swiss Federal Laboratories for Materials Science and
Technology, Überlandstrasse 129, CH-8600 Dübendorf, Switzerland
ABSTRACT
GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors and mid-
IR photodetectors. Here, we investigate the MOCVD growth and properties of GaSb
nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted
selective epitaxy. A high degree of morphological control allows for GaSb nanostructures with
critical dimensions down to 20 nm. Detailed investigation of growth parameters reveals that the
GaSb growth rate is governed by the desorption processes of an Sb surface, and in turn is
insensitive to changes in material transport efficiency. The GaSb crystal structure is typically zinc-
blende with a low density of rotational twin defects and even occasional twin-free structures are
observed. Van der Pauw/Hall measurements are conducted on 20 nm thick GaSb nanostructures,
revealing high hole mobility of 760 cm
2
/Vs, which matches literature values for high-quality bulk
GaSb crystals. Finally, we demonstrate a process that enables cointegration of GaSb and InAs
This document is the accepted manuscript version of the following article:
Borg, M., Schmid, H., Gooth, J., Rossell, M. D., Cutaia, D., Knoedler, M., Bologna, N.,
Wirths, S., Moselund, K. E., & Riel, H. (2017). High-mobility GaSb nanostructures
cointegrated with InAs on Si. ACS Nano, 11(3), 2554-2560.
https://doi.org/10.1021/acsnano.6b04541

nanostructures in close vicinity on Si, a preferred material combination ideally suited for high-
performance complementary III-V MOS technology.
KEYWORDS
GaSb, Template-Assisted Selective Epitaxy, Hole mobility, Cointegration, InAs, Si
The continued miniaturization of complementary metal-oxide-semiconductor (CMOS) circuits has
in recent years demanded alterations of the standard processes such as the incorporation of strained
Si/SiGe channels, high-k metal gate stacks and non-planar device architectures to improve
performance and maintain low power consumption. To be able to continue this progress beyond
the 7 nm node, a shift from Si to III-V semiconductor materials is being considered because of
their high bulk carrier mobilities and injection velocities. However, to become a viable option, III-
V semiconductors have to be fully integrated with standard Si CMOS platforms and processes.
Recently, InGaAs n-type MOS field effect transistors (MOSFETs) integrated with Si CMOS were
successfully demonstrated.
13
For p-type MOSFETs, GaSb is considered a feasible alternative to
Si and SiGe
4
because of its large hole mobility (750-1000 cm
2
/Vs at 300 K) and higher receptivity
to strain.
5
Ga(In)Sb has also been proposed as a potential single material for both p- and n-channel
in III-V CMOS
6
which would allow for a unified device process for both p- and n-devices. In
addition, GaSb is an important material for mid-infrared optoelectronics. At the interface to InAs,
GaSb forms a broken type-II band alignment, successfully utilized as low-noise photodetector
arrays in the mid-IR spectrum.
7
The GaSb/InAs heterojunction is also considered optimal for high-
performance tunnel-FETs,
8,9
devices which may become the successors of MOSFETs in ultra-low-
power electronics. Recently there have been reports of GaSb-on-insulator (-OI) p-MOSFETs by
direct wafer bonding
10
and epitaxial layer transfer,
11
but these methods remain costly due to the
limited sizes of available III-V substrates. The adoption of p-type GaSb in large-scale III-V CMOS

circuits calls for a scalable monolithic integration approach that also allows for cointegration with
high performance n-type materials like InAs and InGaAs. High-quality III-V nanowire devices
have been grown directly on Si(111) substrates by the vapor-liquid-solid and selective area
metalorganic chemical vapor deposition (SA-MOCVD) methods.
1216
However, a recent work
clearly points out that the surface energetics of the antimonide materials pose a fundamental
challenge for realizing well-controlled nanowire-like morphology with small diameter.
17
In this
article, we investigate epitaxial growth of horizontal p-type GaSb-OI nanostructures on Silicon-
OI (SOI) wafers, using a method called Template-Assisted Selective Epitaxy (TASE), based on
SA-MOCVD.
1820
Within TASE, control of the GaSb crystal shape is maintained by confining its
growth within pre-defined oxide templates. Moreover, a high III-V material quality is assured by
minimizing the size of the Si/III-V heterojunction, avoiding both dislocation threading and anti-
phase boundary defects. Electrical characterization of GaSb nano-scale Hall devices reveal a hole
mobility which is on par with bulk values. Finally, we show that the developed GaSb process can
be used for cointegration of GaSb with InAs nanowires on the same wafer, tightly packed right
next to each other.
Results and Discussion
Figure 1a displays a scanning electron microscopy (SEM) image of an exemplary array of
GaSb nanostructures after completed epitaxy, still covered by the oxide templates in which they
were grown. A high tilt-angle SEM image of GaSb nanostructures after template removal is
displayed in Figure 1b. The GaSb crystals are in intimate contact with the Si fins on which endpoint
they nucleated. The shape of the GaSb nanostructures has been defined by the template inner walls,
and cross-sectional dimensions down to 20 nm are routinely achieved. The amount of unwanted
GaSb growth on the mask is typically minute even at the lowest growth temperatures studied.

However, at V/III ratios of 0.6 and below, large (>5 µm diameter) round Ga-rich crystallites
deposit on the mask outside the templates (Supporting information). The exposed front GaSb
surface, at which the crystal grows, typically forms a large {111} facet often with two smaller and
opposing {110} facets (see Figure 1c-d) similar to the case of InAs TASE.
20
Because of the polar
nature of the GaSb zinc-blende crystal structure, non-equivalent 180° rotations of the crystal lattice
can occur upon nucleation on the non-polar Si. This results in two distinct orientations of the
growth facets as illustrated in Figure 1d. It is through growth on these facets that the GaSb
nanostructures fill up the length of the oxide template. In many cases a more varied range of growth
front morphologies are observed, as exemplified in Figures 2a-b. Such growth fronts also correlate
with a higher growth rate. In particular, a roughly 18° in-plane inclination of the growth front is
often observed, corresponding to the orientation of a {112} facet. Facets of higher angles such as
45° (Figure 2b) are common as well. In extreme cases the GaSb only partially fills up the template.
The prevalence of these alternative facet morphologies is correlated with a low nominal V/III ratio
(Figure 2c), suggesting that it may be the consequence of a partial Ga-enrichment on the growth
surface, leading to a local growth rate enhancement and thus the formation of higher-index facets
to accommodate the uneven evolution of the growth front. As shown in Figure 2b and S2, even
Ga-droplet assisted vapor-liquid-solid (VLS) growth is observed.
15,21
Notably, in extreme cases of
Ga-droplet-mediated growth the oxide template still guides the GaSb crystal and therefore still
enables a precisely defined GaSb morphology.

Figure 1. (a) SEM image of an array of horizontal GaSb nanostructures grown at 550 °C
integrated co-planar with a SOI layer using TASE. The inset shows an illustration of the layer
structure. (b-c) SEM images taken at 75° tilt angle of GaSb nanostructures grown at 550 °C. (d)
Schematic illustration highlighting the typical faceting observed at the growth front of the GaSb
crystals.
Figure 2. SEM images of GaSb nanostructures exhibiting variations to the typical growth front,
(a) with an angle to the growth direction, (b) pointy end which only partially fills up the

Figures
Citations
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Selective area epitaxy of III–V nanostructure arrays and networks: Growth, applications, and future directions

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Ultrahigh Hole Mobility of Sn-Catalyzed GaSb Nanowires for High Speed Infrared Photodetectors.

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III-V heterostructure tunnel field-effect transistor.

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References
More filters
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A III–V nanowire channel on silicon for high-performance vertical transistors

TL;DR: Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability.
Journal ArticleDOI

Effects of crystal phase mixing on the electrical properties of InAs nanowires

TL;DR: It is found that mixtures of these phases can exhibit up to 2 orders of magnitude higher resistivity than single-phase nanowires, with a temperature-activated transport mechanism, but it is also found that defects in the form of stacking faults and twin planes do not significantly affect the resistivity.
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Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

TL;DR: In this article, a template-assisted selective epitaxy (TASE) was used to construct 3D stacked nanowires and multiple gate field effect transistors (MuG-FETs) co-planar to the SOI layer.
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A General Approach for Sharp Crystal Phase Switching in InAs, GaAs, InP, and GaP Nanowires Using Only Group V Flow

TL;DR: It is shown that the change in surface energetics of the vapor-liquid-solid system at the vapor -liquid and liquid-solid interface is likely to control the crystal structure in III-V nanowires.
Related Papers (5)
Frequently Asked Questions (16)
Q1. What are the contributions in "High-mobility gasb nanostructures cointegrated with inas on si" ?

Here, the authors investigate the MOCVD growth and properties of GaSb nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted selective epitaxy. Finally, the authors demonstrate a process that enables cointegration of GaSb and InAs This document is the accepted manuscript version of the following article: Borg, M., Schmid, H., Gooth, J., Rossell, M. D., Cutaia, D., Knoedler, M., Bologna, N., Wirths, S., Moselund, K. E., & Riel, H. ( 2017 ). 

The high degree of morphological control together with the exceptional electrical quality of the GaSb nanostructures, as well as the possibility for GaSb cointegration with other III-V materials on Si provides a perfect basis for a wide range of electronic and mid-IR optoelectronic applications integrated with Si CMOS. 

In this cointegration process, an additional important aspect of the oxide templates is to suppress decomposition of the InAs nanowires during GaSb growth, with the template being be a diffusion barrier for volatile As species. 

32 For GaSb, the weak width dependence can be attributed to the high surface coverage of Sb, such that a variation in material supply will have only a minor effect on the growth rate if any at all. 

When a short InAs segment (<20 nm long) was grown first, the GaSb nucleation yield decreased much more slowly with increased V/III ratio, and even at V/III ratios above 3 the yield is still around 25%. 

The GaSb crystal grows along the [110] direction, and (111) rotational twin and stacking faults are observed edge-on at a lower density (0.2 defects/nm) compared to what is commonly observed in GaAs and InAs TASE (> 1 defects/nm).33 

The high degree of morphological control together with the exceptional electrical quality of the GaSb nanostructures, as well as the possibility for GaSb cointegration with other III-V materials on Si provides a perfect basis for a wide range of electronic and mid-IR optoelectronic applications integrated with Si CMOS. 

15,21 Notably, in extreme cases of Ga-droplet-mediated growth the oxide template still guides the GaSb crystal and therefore still enables a precisely defined GaSb morphology. 

The colored map in Figure 6d is generated using pink for In and As, and orange for Ga and Sb. Detailed investigation of the InAs crossection by EDS reveal no visible material degradation, and Hall measurements confirm that the electron mobility in co-integrated InAs devices is unaffected by the cointegration processa particular feature of TASE which can be extended also to other material systems, even other than III-V, without significant alterations. 

The prevalence of these alternative facet morphologies is correlated with a low nominal V/III ratio (Figure 2c), suggesting that it may be the consequence of a partial Ga-enrichment on the growth surface, leading to a local growth rate enhancement and thus the formation of higher-index facets to accommodate the uneven evolution of the growth front. 

The authors observe that the yield of GaSb nucleation in the oxide templates strongly depends on the nominal V/III ratio, as displayed in Figure 3a. 

Sb surface layer in the initial phase of growth could account for the reduced nucleation yield observed for higher V/III ratios (Figure 3a). 

The shape of the GaSb nanostructures has been defined by the template inner walls, and cross-sectional dimensions down to 20 nm are routinely achieved. 

A decrease in growth rate with increasing V/III ratio was previously observed for MOCVD of GaSb(100) under Sb-rich conditions,22 although the effect was much weaker. 

34 Figure 4a displays an atomically resolved high-angle annular dark-field (HAADF) STEM image along the [-110] viewing direction of a GaSb crystal grown at a V/III ratio of 0.4 at a temperature of 550 °C. 

To investigate this hypothesis further the temperature dependence in the range from 510 °C to 585 °C of the GaSb growth rate was studied at relatively high V/III ratio (1.2).