Journal ArticleDOI
Improvement in analog/RF performances of SOI TFET using dielectric pocket
TLDR
In this paper, the impact of dielectric pocket on analog/radio-frequency (RF) performances of SOI-TFET was investigated, and it was found that the inclusion of a Dielectric Pocket to SOI -TFET has been found to have...Abstract:
In this manuscript, the impact of dielectric pocket on analog/radio-frequency (RF) performances of SOI-TFET is investigated. The inclusion of a dielectric pocket to SOI-TFET has been found to have ...read more
Citations
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Journal ArticleDOI
Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications
TL;DR: In this article, the temperature dependence of 10-nm junctionless (JL) nanosheet FET performance on DC and analog/RF characteristics are investigated for the first time using extended source/drain and with high-k gate stack.
Journal ArticleDOI
Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters
TL;DR: In this article , a novel structure of GAA vertical TFET (GAA-VTFET) is proposed and investigated with the help of 3D TCAD simulator, which offers much improvement in various DC parameters like ION, IOFF, SSAVG, and turn-on voltage (VT) compared to a conventional GAA-TFET.
Journal ArticleDOI
Junctionless Gate-All-Around Nanowire FET with Asymmetric Spacer for Continued Scaling
TL;DR: In this article, the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10-nm gate length (LG) has been studied and various DC metrics like subthreshold swing (SS), drain induced barrier lowering (DIBL), ION/IOFF ratio are discussed.
Journal ArticleDOI
Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes
TL;DR: In this article, a dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects in DG MOSFETs.
Journal ArticleDOI
Design and Investigation of F-Shaped Tunnel FET With Enhanced Analog/RF Parameters
TL;DR: In this article, a physically doped single gate F-shaped tunnel FET is simulated and optimized for different source thickness, source length, drain length with different lateral tunneling lengths between the source edge and gate dielectric.
References
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Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Tunnel field-effect transistor without gate-drain overlap
TL;DR: In this article, the authors generalized the tunnel field effect transistor configuration by allowing a shorter gate structure, which is especially attractive for vertical nanowire-based transistors, and demonstrated with device simulations that the more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
Journal ArticleDOI
Hetero-Gate-Dielectric Tunneling Field-Effect Transistors
Woo Young Choi,Woojun Lee +1 more
TL;DR: In this article, the authors proposed a hetero-gate-dielectric TFET, which enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.