scispace - formally typeset
U

Umakanta Nanda

Researcher at VIT University

Publications -  71
Citations -  539

Umakanta Nanda is an academic researcher from VIT University. The author has contributed to research in topics: Phase-locked loop & Phase noise. The author has an hindex of 8, co-authored 48 publications receiving 213 citations. Previous affiliations of Umakanta Nanda include National Institute of Technology, Rourkela & Silicon Institute of Technology.

Papers
More filters
Journal ArticleDOI

Clinical characteristics with inflammation profiling of long COVID and association with 1-year recovery following hospitalisation in the UK: a prospective observational study

Tracy Hussell, +527 more
- 01 Aug 2022 - 
TL;DR: The Post-hospitalisation COVID-19 study (PHOSP-COVID) as mentioned in this paper is a prospective, longitudinal cohort study recruiting adults (aged ≥18 years) discharged from hospital with COVID19 across the UK.
Proceedings ArticleDOI

Universal Asynchronous Receiver and Transmitter (UART)

Umakanta Nanda, +1 more
TL;DR: UART is implemented in virtex II pro FPGA chip due to low cost, high speed, reprogram ability and fast time to market.
Journal ArticleDOI

A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate

Debasish Nayak, +3 more
- 01 Mar 2018 - 
TL;DR: The proposed highly stable 8T-SRAM cell is capable to be arranged in a bit-interleaving fashion which can then use a conventional error correction code (ECC) to correct the single bit error caused by the exposer to cosmic radiation.
Journal ArticleDOI

Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction

Avtar Singh, +2 more
- 01 Jul 2022 - 
TL;DR: In this paper , a high-k dielectric pocket is placed at the drain side to improve DC performance of the device, which reduces the ambipolar current up to a large extent.
Journal ArticleDOI

Design of an efficient phase frequency detector to reduce blind zone in a PLL

Umakanta Nanda, +2 more
- 01 Mar 2017 - 
TL;DR: In this paper, a variable delay element is incorporated in the reset path of the phase frequency detector (PFD) to avoid the blind zone at lower phase noise, and the overall PFD delay is maintained at a small positive value.