Proceedings ArticleDOI
Investigation of nanowire size dependency on TSNWFET
Sung Dae Suk,Ming Li,Yun Young Yeoh,Kyoung Hwan Yeo,Keun Hwi Cho,In Kyung Ku,H.-J. Cho,Won-Jun Jang,Dong-Won Kim,Donggun Park,Won-Seong Lee +10 more
- pp 891-894
TLDR
In this paper, the authors investigated the performance of nanowire transistor and found that 4 nm is the best point to maximize the volume inversion effect on gate all around nanowires MOSFET.Abstract:
Nanowire size (dNW) dependency of various electrical characteristics on gate all around twin silicon nanowire MOSFET (TSNWFET) is investigated to understand overall performance of nanowire transistor deeply. When dNW decreases, current drivability (Ion) normalized by circumference at the same VG-VTH improves and maximizes at dNW of 4 nm. And mobility is also estimated with capacitance and series resistance. All the experimental investigation shows that dNW of 4 nm is the best point to maximize the volume inversion effect on gate all around nanowire MOSFET.read more
Citations
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Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Journal ArticleDOI
Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs
TL;DR: In this paper, experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length.
Journal ArticleDOI
Scaling of Nanowire Transistors
TL;DR: In this article, the scaling of nanowire transistors to 10-nm gate lengths and below is considered and compared with the published experimental data of nan-wire transistors, and the performance limit of a nan-ire transistor is assessed by applying a ballistic current model.
Patent
Nanowire Mesh FET with Multiple Threshold Voltages
TL;DR: In this paper, a nanowire-based field effect transistors (FETs) and techniques for the fabrication thereof are provided, where each FET has a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality OF channels connecting the source region and the drain region.
Journal ArticleDOI
Quantum-Transport Study on the Impact of Channel Length and Cross Sections on Variability Induced by Random Discrete Dopants in Narrow Gate-All-Around Silicon Nanowire Transistors
TL;DR: In this paper, the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors has been investigated using the nonequilibrium Green's function formalism.