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UC Berkeley Previously Published Works
Title
MoS2 transistors with 1-nanometer gate lengths.
Permalink
https://escholarship.org/uc/item/5157q7f4
Journal
Science (New York, N.Y.), 354(6308)
ISSN
0036-8075
Authors
Desai, Sujay B
Madhvapathy, Surabhi R
Sachid, Angada B
et al.
Publication Date
2016-10-01
DOI
10.1126/science.aah4698
Peer reviewed
eScholarship.org Powered by the California Digital Library
University of California
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ACK NOW LE DGM EN TS
We thank M. Baranov, F. Schreck, G. Bruun, N. Davidson, and
R. Folman for stimulating discussions. Supported by NSF through
a grant for ITAMP at Harvard University and the Smithsonian
Astrophysical Observatory (R.S.); the Technical University of
Munich-Institute for Advanced Study, funded by the German
Excellence Initiative and the European Union FP7 under grant
agreement 291763 (M.K.); the Harvard-MIT Center for Ultracold
Atoms, NSF grant DMR-1308435, the Air Force Office of Scientific
Research Quantum Simulation Multidisciplinary University
Research Initiative (MURI), the Army Research Office MURI on
Atomtronics, M. Rössler, the Walter Haefner Foundation, the ETH
Foundation, and the Simons Foundation (E.D.); and the Austrian
Science Fund (FWF) within the SFB FoQuS (F4004-N23) and
within the DK ALM (W1259-N27).
SUPPLEMENTARY MATERIALS
www.sciencemag.org/content/354/6308/96/suppl/DC1
Materials and Methods
Supplementary Text
Figs. S1 to S11
Table S1
References (34–56)
20 February 2016; accepted 6 September 2016
10.1126/science.aaf5134
DEVICE TECHNOLOGY
MoS
2
transistors with 1-nanometer
gate lengths
Sujay B. Desai,
1,2,3
Surabhi R. Madhvapathy,
1,2
Angada B. Sachid,
1,2
Juan Pablo Llinas,
1,2
Qingxiao Wang,
4
Geun Ho Ahn,
1,2
Gregory Pitner,
5
Moon J. Kim,
4
Jeffrey Bokor,
1,2
Chenming Hu,
1
H.-S. Philip Wong,
5
Ali Javey
1,2,3
*
Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate
lengths because of severe short channel effects. As an a lternative to S i, certain layered
semiconductors are attractive for their atomically uniform thickness down to a
monolayer, lower dielectric constants, larger band ga ps, and heavier carrier effective
mass. Here, we demonstrate molybdenum disulfide (MoS
2
) transistors with a 1-nm
physical gate length using a single-walled carbon nanotube as the gate electrode. These
ultrashort dev ices exhibit excellent switching chara cteristics with near ideal
subthreshold swing of ~65 millivolts per decade and an On/Off current ra tio of
~10
6
. Simulations show an effective channel length of ~3.9 nm in the Off state and
~1 nm in the On state.
A
s Si transistors rapidly approach their pro-
jected scaling limit of ~5-nm gate lengths,
exploration of new channel materials and
device architectures is of utmost interest
(1–3). This scaling limit arises from short
channel effects (4). Direct source-to-drain tunnel-
ing and the loss of gate electrostatic control on the
channel severely degrade the Off state leakage cur-
rents, thus limiting the scaling of Si transistors
(5, 6). Certain semiconductor properties dictate
the magnitude of these effects for a given gate
length. Heavier carrier effective mass, larger
band gap, and lower in-plane dielectric constant
yield lower direct source-to-drain tunneling cur-
rents (7). Uniform and atomically thi n semicon-
ductors with low in-plane dielectric constants
are desirable for enhanced electrostatic control
of the gate. Thus, investigation and introduc-
tion of semiconductors that have more ideal prop-
erties than Si could lead to further scaling of
transistor dimensions with lower Off state dis-
sipation power.
Transition metal dichalcogenides (TMDs) are
layered two-dimensional (2D) semiconductors
that have been widely explored as a potential
channel material replacement for Si (8–11), and
each material exhibits different band struc-
tures and properties (12–16). The layered nature
of TMDs allows uniform thicknes s co ntrol with
atomic-level precision down to the monolayer
limit. This thickness scaling feature of TMDs
is highly desirable for well-controlled electro-
statics in ultrashort transistors (3). For example,
monolayer and few-layer MoS
2
have been shown
theoretically to be superior to Si at the sub-5-nm
scaling limit (17, 18).
The scaling characteristics of MoS
2
and Si tran-
sistors as a function of channel thickness and gate
length are summarized in Fig. 1. We calculated
direct source-to-drain tunneling currents (I
SD-LEAK
)
in the Off state for different channel lengths and
thicknesses using a dual-gate device structure (fig.
S1)asameanstocomparethetwomaterials.MoS
2
shows more than two orders of magnitude reduc-
tion in I
SD-LEAK
relative to Si mainly because of
its larger electron effective mass along the trans-
port direction (m
*
n
∼ 0:55m
0
for MoS
2
versus
m
*
n
∼ 0:19m
0
for Si [100]) (19), with a trade-off
resulting in lower ballistic On current. Notably,
I
SD-LEAK
does not limit the scaling of monolayer
MoS
2
even down to the ~1-nm gate length, pre-
senting a major advantage over Si [see more de-
tails about calculations in the supplementary
materials (20)]. Finally, few-layer MoS
2
exhibits a
lower in-plane dielectric constant (~4) compared
with bulk Si (~11.7), Ge (~16.2), and GaAs (~12.9),
resulting in a shorter electrostatic characteristic
length (l)asdepictedinfig.S2(21).
TheabovequalitiescollectivelymakeMoS
2
a
strong candidate for the channel material of fu-
ture transistors at the sub-5-nm scaling limit.
However, to date, TMD transistors at such small
gate lengths have not been experimentally ex-
plored. Here, we demonstrate 1D gated, 2D semi-
conductor field-effect transistors (1D2D-FETs) with
a single-walled carbon nanotube (SWCNT) gate,
aMoS
2
channel, and physical gate lengths of ~1 nm.
The 1D2D-FETs exhibit near ideal switching char-
acteristics, including a subthreshold swing (SS) of
~65 mV per decade at room temperature and high
On/Off current ratios. The SWCNT diameter d ~
1nmforthegateelectrode(22) minimized par-
asitic gate to source-drain capacitance, which is
characteristic of lithographically patterned tall
gate structures. The ~1-nm gate length of the SWCNT
also allowed for the experimental exploration of
the device physics and properties of MoS
2
tran-
sistors as a function of semiconductor thickness
(i.e., number of layers) at the ultimate gate-length
scaling limit.
The experimental device structure of the 1D2D-
FET (Fig. 2A) consists of a MoS
2
channel (number
of layers vary), a ZrO
2
gate dielectric, and a SWCNT
gate on a 50-nm SiO
2
/Si substrate with a physi-
cal gate length (L
G
~ d)of~1nm.Long,aligned
SWCNTs grown by chemical vapor deposition
SCIENCE sciencemag.org 7 OCTOBER 2016 • VOL 354 ISSUE 6308 99
1
Electrical Engineering and Computer Sciences, University of
California, Berkeley, CA 94720, USA.
2
Materials Sciences
Division, Lawrence Berkeley National Laboratory, Berkeley,
CA 94720, USA.
3
Berkeley Sensor and Actuator Center,
University of California, Berkeley, CA 94720, USA.
4
Department of Materials Science and Engineering,
University of Texas at Dallas, Richardson, TX 75080, USA.
5
Electrical Engineering, Stanford University, Stanford, CA
94305, USA.
*Corresponding author. Email: ajavey@eecs.berkeley.edu
RESEARCH
| REPORTS
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were transferred onto a n
+
Si/SiO
2
substrate
(50-nm-thick SiO
2
)(23), located with a scanning
electron microsco pe (SEM), and contacted with
palladium via lithography and metallization. These
steps were followed by atomic layer deposition
(ALD) of ZrO
2
and pick-and-place dry transfer of
MoS
2
onto the SWCNT covered by ZrO
2
(14).
Nickel source and drain contacts were made to
MoS
2
to complete the device. The detailed pro-
cess flow and discussion about device fabrication
is provided in fig. S3.
Figure 2B shows the optic al image of a repre-
sentative 1D2D-FET capturing the MoS
2
flake, the
source and drain contacts to MoS
2
,andthegate
contacts to the SWCNT. The SWCNT and the MoS
2
flake can be identified in the false-colored SEM
image of a representative sample (Fig. 2C). The
1D2D-FET consists of four electrical terminals;
source (S), drain (D), SWCNT gate (G), and the n
+
Si substrate back gate (B). The SWCNT gate un-
derlaps the S/D contacts. These underlapped re-
gions were electrostatically doped by the Si back
gate during the electrical measurements, thereby
serving as n
+
extension contact regions. The de-
vice effectively operated like a junctionless tran-
sistor (24), where the SWCNT gate locally depleted
the n
+
MoS
2
channel after applying a negative
voltage, thus turning Off the device.
A cross-sectional transmission electron micro-
scope(TEM)imageofarepresentative1D2D-
FET (Fig. 2D) shows the SWCNT gate, ZrO
2
gate
dielectric (thickness T
OX
~5.8 nm), and the bilayer
MoS
2
channel. The topography of ZrO
2
surround-
ing the SWCNT and the MoS
2
flake on top of the
gate oxide was flat, as seen in the TEM image. This
geometry is consistent with ALD nucleation ini-
tiating on the SiO
2
substrate surrounding the
SWCNT and eventually covering it completely as
the thickness of deposited ZrO
2
exceeds the SWCNT
diameter d (25). The spatial distribution of carbon,
zirconium, and sulfur was observed in the electron
energy-loss spectroscopy (EELS) map of the de-
vice region (Fig. 2E), thus confirming the loca-
tion of the SWCNT, ZrO
2
,andMoS
2
in the device
(fig. S4) (20).
The electrical characteristics for a 1D2D-FET
with a bilayer MoS
2
channel (Fig. 3) show that the
MoS
2
extension regions (the underlapped regions
between the SWCNT gate and S/D contacts) could
be heavily inverted (i.e., n
+
state) by applying a
positive back-gate voltage of V
BS
= 5 V to the Si
substrate. The I
D
-V
BS
characteristics (fig. S5)
indicate that the MoS
2
flake was strongly in-
verted by the back gate at V
BS
= 5 V. The I
D
-V
GS
characteristics for the device at V
BS
=5VandV
DS
=
50 mV and 1 V (Fig. 3A) demonstrate the ability of
the ~1-nm SWCNT gate to deplete the MoS
2
chan-
nel and turn Off the device. The 1D2D-FET exhib-
ited excellent subthreshold characteristics with
a near ideal SS of ~65 mV per decade at room
tem perature and On/Off current ratio of ~10
6
.
The drain-induced barrier lowering (DIBL) was
~290 mV/V. Leakage currents through the SWCNT
gate (I
G
)andthen
+
Si back gate (I
B
)areatthe
measurement noise level (Fig. 3A). The interface
trap density (D
IT
) of the ZrO
2
-MoS
2
interface
estimated from SS was ~1.7 × 10
12
cm
−2
eV
−1
,
100 7 OCT OBER 2016 • VOL 354 ISSUE 6308 sciencemag.org SCIE NCE
123
10
-14
10
-12
10
-10
10
-8
10
-6
10
-4
MoS
2
I
SD-LEAK
(A/µm)
T
CH
(nm)
V
GS
- V
FB
= 0 V (OFF)
V
DS
= 0.43 V
Si
T
OX
= 0.5 nm
ε
OX,
y
= 3.9 ε
0
L
G
= 4 nm
3456
10
-20
10
-17
10
-14
10
-11
10
-8
10
-5
T
CH
(nm)
Si:
2.17, 1.08
MoS
2
: 1.3, 0.65
I
SD-LEAK
(A/µm)
L
G
(nm)
Low power technology
limit
Fig. 1. Direct source-to-drain tunneling leakage current. (A) Normalized direct source-to-drain tunnel-
ing leakage curr ent (I
SD-LEAK
), calculated using the WKB (We ntz el-Kr amers-Brillouin) approximation as a
function of channel thickness T
CH
for Si and MoS
2
in the Off state. V
DS
= V
DD
= 0.43 V from the International
Technology Roadmap for Semiconductors (ITRS) 2026 technology node. (B) I
SD-LEAK
as a function of gate
length L
G
for differ ent thicknesses of Si and MoS
2
for the same Off state conditions as Fig. 1A. The dotted
line in Fig. 1, A and B repr esents the low operating pow er limit for the 2026 technology node as specified by
the ITRS.
Fig. 2. 1D2D-FET device structure and characterization. (A) Schematic of 1D2D-FET with a MoS
2
channel and SWCNT gate. (B) Optical image of a r epr esentat iv e device shows the MoS
2
flake, gate (G),
source (S), and drain (D) electrodes. (C) False-colored SEM image of the de vice showing the SWCNT
(blue), ZrO
2
gate dielectric (green), MoS
2
channel (orange ), and the Ni source and dr ain electrode s
(yello w). (D) Cross-sectional TEM image of a repr esentativ e sample showing the SWCNT gate, ZrO
2
gate
dielectric, and bilayer MoS
2
channel. (E) EELS map showing spatial distribution of carbon, zir conium, and
sulfur in the device region, confirming the location of the SWCNT, MoS
2
flake, and ZrO
2
dielectric.
RESEARCH | REPORTS
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which is typical for transferred MoS
2
flakes
(26) because of the absence of surface dangling
bonds (20).
Figure 3B shows the I
D
-V
DS
characteristics at
different V
GS
values and fixed V
BS
=5V.TheI
D
-
V
GS
characteristics depended strongly on the
value of V
BS
, which affects the extension region
resistance. The inversion of the extension regions
increased with increasing V
BS
, thus reducing the
series resistance and contact resistance and led
to an increase in the On current and an improve-
ment in the SS. At more positive values of V
BS
, V
GS
hadtobemorenegativeinordertodepletethe
MoS
2
channel,whichinturnmadethethreshold
voltage (V
T
)morenegative.AboveV
BS
=1V,theSS
and I
On
did not improve any further , and the ex-
tension regions were strongly inverted (Fig. 3C). Thus,
the 1D2D-FET operated as a short-channel device.
We performed detailed simulations using Sen-
taurus TCAD to understand the electrostatics of
the 1D2D-FET. The Off and On state conditions
correspond to (V
GS
-V
T
)of–0.3 V and 1.5 V, re-
spectively (which give an On/Off current ratio of
~10
6
). The electric field contour plot (Fig. 3D) in
the Off state has a region of low electric field in
the MoS
2
channel near the SWCNT, indicating
that it is depleted. The reduced electron density
in the MoS
2
channel (Fig. 3E), and the presence
of an energy barrier to electrons in the conduc-
tion band (fig. S6A) are also consistent with the
Off state of the device. The extension regions are
still under inversion because of the positive back-
gate voltage. The electron density of the MoS
2
channel in the depletion region can be used to
define the effective channel length (L
EFF
)ofthe
1D2D-FET, which is the region of channel con-
trolled by the SWCNT gate (27–29). The channel
is considered to be depleted if the electron den-
sity falls below a defined threshold (n
threshold
).
The Off state L
EFF
, defined as the region of MoS
2
with electron density n < n
threshold
(n
threshold
=1.3×
10
5
cm
−2
), for this simulated 1D2D-FET is L
EFF
~
3.9 nm (Fig. 3E). L
EFF
is dependent on V
GS
and the
value of n
threshold
(fig. S7).
As the device is turned Off, the fringing electric
fields from the SWCNT (Fig. 3D) deplete farther
regions of the MoS
2
channel and thus increase
L
EFF
. The short height of the naturally defined
SWCNT gate prevents large fringing fields from
controlling the channel and hence achieves a
smaller L
EFF
compared with lithographically pat-
terned gates (fig. S8). The electric field and elec-
tron density contours for the device in the On
state confirm the strong inversion of the channel
region near the SWCNT (Fig. 3, F and G) with
L
EFF
~ L
G
= 1 nm. The energy bands in this case
are flat in the entire channel region (fig. S6B),
with the On state current being limited by the
resistance of the extension regions and mainly
the contacts. Doped S/D contacts along with
shorter extension regions will result in increased
On current.
The effec t of T
OX
scaling on short-channel
effects like DIBL was also studied using simu-
lations (fig. S9). The electrostatics of the device
improves, and the influence of the drain on the
channel reduces, as T
OX
is scaled down to values
SCIENCE sciencemag.org 7 OCTOB ER 2016 • VOL 354 ISSUE 6308 101
-3 -2 -1 0 1
10
-12
10
-10
10
-8
10
-6
10
-4
V
DS
= 1 V
I
D
(A/µm)
V
GS
(V)
V
BS
-5 V
-3 V
-1 V
1 V
5 V
0.0 0.5 1.0 1.5 2.0 2.5
0
5
10
15
20
25
30
V
GS
= -3 V to 0.5 V
Step = 0.5 V
V
BS
= 5 V
I
D
(µA/µm)
V
DS
(V)
-3 -2 -1 0 1
10
-12
10
-10
10
-8
10
-6
10
-4
I
G
, I
B
V
DS
= 50 mV
V
DS
= 1 V
I
D
(A/µm)
V
GS
(V)
V
BS
= 5 V
65 mV/decade
e
-
density (cm
-2
)
6.5 x 10
12
2.1 x 10
9
1.3 x 10
5
SiO
2
ZrO
2
MoS
2
ON
L
EFF
~ 3.9 nm
SiO
2
ZrO
2
MoS
2
OFF
(MV/cm)
5.7
2.9
0.001
SiO
2
ZrO
2
MoS
2
ON
4 nm
SiO
2
ZrO
2
MoS
2
OFF
4 nm
4 nm 4 nm
SWCNT
SWCNT
Fig. 3. Electrical characterization and TCAD simulations of 1D2D-FET. (A) I
D
-V
GS
characteristics of a
bilayer MoS
2
channel SWCNT gated FET at V
BS
=5VandV
DS
= 50 mV and 1 V. The positive V
BS
voltage
electrostatically dopes the extension regions n
+
.(B) I
D
-V
DS
characteristic for the device at V
BS
=5Vand
varying V
GS
.(C) I
D
-V
GS
characteristics at V
DS
=1VandvaryingV
BS
illustrating the effect of back-g ate bias
on the extension region re sistance, SS, On current, and device characteristics. Electric field contour plots
for a simulated bilayer MoS
2
device using TC AD in the (D)Offand(F)Onstate.Electrondensityplotsfor
the simulated device using TCAD in the (E)Offand(G) On state. The electron density in the depletion
region is used to define the L
EFF
. L
EFF
~ d ~ L
G
in the On state and L
EFF
> L
G
intheOffstatebecauseofthe
fringing electric fields from the SW C NTgate.
024681012
0
40
80
120
160
200
Simulation
Experiment
V
DS
= 1 V
V
BS
= 5 V
Subthreshold Swing (mV/dec)
MoS
2
thickness (nm)
-2 -1 0 1 2
10
-13
10
-11
10
-9
10
-7
10
-5
I
D
(A/µm)
V
GS
-V
T
(V)
V
BS
= 5 V
V
DS
= 1 V
MoS
2
thickness
1.3 nm
12 nm
31 nm
Fig. 4. MoS
2
thickness dependence. (A) Dependence of MoS
2
channel thickness on the performance of
1D2D-FET. SS increases with increasing MoS
2
channel thickness. (B) Extracted SS from experimental
curves and TC AD simulations show incr easing SS as channel thickness T
CH
increases.
RESEARCH | REPORTS
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commensurate with L
G
. This effect is seen by the
strong dependence of DIBL on T
OX
,thusdemon-
strating the need f or T
OX
scaling and high-k
(dielectric constant) 2D dielectrics to further
enhance the device performance.
The effec t of MoS
2
thickness on the device
characteristics was systematically explored. At the
scaling limit of the gate length, the semiconductor
channel thickness must also be scaled down ag-
gressively, as described earlier . The electrostatic
control of the SWCNT gate on the Mo S
2
channel
decreased with increasing distance from the ZrO
2
-
MoS
2
interface. Thus, as the MoS
2
flake thickness
was increased, the channelcouldnotbecomplete-
ly depleted by applying a negative V
GS
.Becauseof
this effect, the SS for a 12-nm-thick MoS
2
device
(~170 mV per decade) was much larger than that
of bilayer MoS
2
(~65 mV per decade), and as the
thicknes s of MoS
2
was increased to ~31 nm, the
device could no longer be turned off (Fig. 4A).
The experimental SS as a function of MoS
2
thick-
ness was qualitatively consistent with the TCAD
simulations (Fig. 4B and S10), showing an in-
creasing trend with increasing channel thickness.
The unwanted variations in device performance
caused by channel thickness fluctuations (Fig. 4B
and fig. S10), and the need for low Off state cur-
rent at short channel lengths (Figs. 1 and 3), thus
justify the need for layered semiconduc tors like
TMDs at the scaling limit.
TMDs offer the ultimate scaling of thickness
with atomic-level control, and the 1D2D-FET
structure enables the study of their physics and
electrostatics at short channel lengths by using
the natural dimensions of a SWCNT, removing
the need for any lithography or patterning pro-
cesses that are challenging at these scale lengths.
However, large-scale processing and manufac-
turing of TMD devices down to such small gate
lengths are existing challenges requiring future
innovations. For instance, research on develop-
ing process-stable, low-resistance ohmic contacts
to TMDs, and scaling of the gate dielectric by
using high-k 2D insulators is essential to further
enhance device performance. Wafer-scale growth
of high-quality films (30) is another challenge
toward achieving very-large-scale integration of
TMDs in integrated circuits. Finally, fabrication
of electrodes at such small scale lengths over large
areas requires considerable advances in litho-
graphic techniques. Nevertheless, the work here
provides new insight into the ultimate scaling of
gate lengths for a FET by surpassing the 5-nm
limit (3–7) often associated with Si technology.
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ACK NOW LE DGM EN TS
S.B.D. and A.J. were supported by the Electronics Materials
program funded by the Director, Office of Science, Office of Basic
Energy Sciences, Materials Sciences and Engineering Division of
the U.S. Department of Energy under contract DE-AC02-
05CH11231. A.B.S. was funded by Applied Materials, Inc., and
Entegris, Inc., under the I-RiCE program. J.P.L. and J.B. were
supported in part by the Office of Naval Research BRC program.
J.P.L. acknowledges a Berkeley Fellowship f or Graduate Studies
and the NSF Graduate Fellowship Program. Q.W. and M.J.K. were
supported by the NRI SWAN Center and Chinese Academy of
Sciences President’s International Fellowship Initiative
(2015VTA031). G.P. and H.-S.P.W. were supported in part by the
SONIC Research Center, one of six centers supported by the
STARnet phase of the Focus Center Research Program (FCRP) a
Semiconductor Research Corporation program sponsored by
MARCO and DARPA. A.J., H.-S.P.W., and J.B. acknowledge the NSF
Center for Energy Efficient Electronics Science (E
3
S). A.J.
acknowledges support from Samsung. The authors acknowledge
the Molecular Foundry, Lawrence Berkeley National Laboratory for
access to the scanning electron microscope. The authors acknowledge
H. Fahad for useful discussions about the analytical modeling. All data
are reported in the main text and supplementary materials.
SUPPLEMENTARY MATERIALS
www.sciencemag.org/content/354/6308/99/suppl/DC1
Materials and Methods
Supplementary Text
Figs. S1 to S10
Table S1
References (31–44)
30 June 2016; accepted 7 September 2016
10.1126/science.aah4698
BIOCATALYSIS
An artificial metalloenzyme with the
kinetics of native enzymes
P. Dydio,
1,2
* H. M. Key,
1,2
* A. Nazarenko,
1
J. Y.-E. Rha,
1
V. Seyedkazemi,
1
D. S. Clark,
3,4
J. F. Hartwig
1,2
†
Natural enzymes contain highly ev olved active sites that lead to fast rates and high selectivities.
Although artificial metalloenzymes have been developed that catalyze abiological
transform ations with high stereoselectivity, the activities of these artificial enzymes are
much lower than those of natural enzymes. Here , we report a reconstituted artificial
metalloenzyme containing an iridium porphyrin that exhibits kinetic parameters similar to
those of natural enzymes. In particular , variants of the P450 enzyme CYP119 containing iridium
in place of iron catalyze insertions of carbenes into C–H bonds with up to 98% enantiomeric
ex cess, 35, 000 turnov er s, and 2550 hours
−1
turnov er frequency. This activity leads to
intramolecular carbene insertions into unactivated C–H bonds and intermolecular carbene
insertions into C–H bonds. These results lift the restriction s on merging chemical
catalysis and biocatalysis to create highly active, productive , and selective metalloenzymes
for abiological reactions.
T
he catalytic activity of a metalloenzyme is
determined by both the primary coordina-
tion sphere of the metal and the surrounding
protein sc affold. In some cases, laboratory
evolution has been used to develop variants
of native metalloenzymes for selective reactions
of unnatural substrates (1, 2). Yet with few ex-
ceptions (3), the classes of reactions that such
enzymes undergo are limited to those of bio-
logical transformations. To combine the favorable
qualities of enzymes with the diverse reactivity of
synthetic transition-metal catalysts, abiological
transition-metal centers or cofactors have been
incorporated into native proteins. The resulting
artificial metalloenzymes catalyze classes of re-
actions for which there is no known enzyme
(abiological transformations) (3 , 4).
Although the reactivity of these artificial sys-
tems is new for an enzyme, the rates of these
reactions have been much slower and the
102 7 OCTOBER 2016 • VOL 354 ISSUE 6308 sciencemag.org SCIE NCE
1
Department of Chemistry, University of California, Berkeley,
CA 94720, USA.
2
Chemical Sciences Division, Lawrence
Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA
94720, USA.
3
Department of Chemical and Biomolecular
Engineering, University of California, Berkeley, CA 94720,
USA.
4
Molecular Biophysics and Integrated Bioimaging
Division, Lawrence Berkeley National Laboratory, 1 Cyclotron
Road, Berkeley, CA 94720, USA.
*These authors contributed equally to this work. †Corresponding
author. Email: jhartwig@berkeley.edu
RESEARCH
| REPORTS
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