Journal ArticleDOI
New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
Ming-Dou Ker,Po-Yen Chiu +1 more
TLDR
In this paper, a low-leakage power-rail electrostatic discharge clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process.Abstract:
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit and the ESD clamp device of a substrate-triggered silicon-controlled rectifier, the new proposed power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has a very low leakage current of only 116 nA at room temperature (25°C ) under the power-supply voltage of 1 V. Moreover, the new proposed power-rail ESD clamp circuit can achieve ESD robustness of over 8 kV, 800 V, and over 2 kV in human-body-model, machine-model, and charged-device-model ESD tests, respectively.read more
Citations
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Proceedings Article
A low leakage low cost-PMOS based power supply clamp with active feedback for ESD protection in 65nm CMOS technologies
TL;DR: In this article, a PMOS-based power supply protection clamp is presented which is designed to operate in a 65 nm, low leakage CMOS process and is shown to be amenable to the inherent challenges posed by low cost I/O transistors.
Journal ArticleDOI
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
Chih-Ting Yeh,Ming-Dou Ker +1 more
TL;DR: In this article, a resistorless power-rail ESD clamp circuit realized with only thin-gate-oxide devices and with a silicon-controlled rectifier (SCR) as the main EC clamp device has been proposed and verified in a 65-nm CMOS process.
Journal ArticleDOI
On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
Ming-Dou Ker,Chih-Ting Yeh +1 more
TL;DR: In this paper, the design of power-rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed and compared.
Journal ArticleDOI
An nMOS Static ESD Power Supply Clamp With Thyristor Delay Element and 180 pA Leakage in 65 nm CMOS Technology
TL;DR: In this article, a low-leakage, static ESD clamp is proposed in 65-nm CMOS technology, where the CMOS thyristor was added as a delay element to the conventional diode triggered static clamp to improve its on time during the ESD stress.
Proceedings ArticleDOI
Novel electrostatic discharge (ESD) clamp circuit with low leakage current
TL;DR: In this article, a novel electrostatic discharge clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process.
References
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Journal ArticleDOI
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Journal ArticleDOI
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TL;DR: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented and the solutions to overcome latchup issue in the SCR-based devices are discussed.
Proceedings ArticleDOI
BSIM4 gate leakage model including source-drain partition
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Chih-Ting Yeh,Ming-Dou Ker +1 more