Journal ArticleDOI
Oxidation of silicon nanowires
TLDR
In this paper, the oxidation of silicon nanowires with an average radius of 37nm was investigated using the vapor-liquid-solid technique with Au to mediate the growth of the nanowire.Abstract:
Silicon nanowires have received attention for nanoscale electronic devices and chemical and biological sensors. The thermal oxide grown on the silicon nanowires could be used in a variety of devices, so the oxidation of the silicon nanowires is investigated in this work. Silicon nanowires with an average radius of 37nm were grown for these experiments using the vapor-liquid-solid technique with Au to mediate the growth. Etching of the Au tips from the silicon nanowires was performed prior to oxidation to avoid local accelerated oxidation at the nanowire tip. Oxidation was performed at 700°C for 1–121h and at 650 and 750°C for 4h in O2, and the oxidized nanowires were examined by transmission electron microscopy. Depending on the conditions for oxidation, an oxide shell as thin as 6nm was observed, or the entire nanowire was oxidized. The kinetics of oxidation differ from those of a planar silicon wafer and are discussed in this work.read more
Citations
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Synthesis of Vertical High-Density Epitaxial Si(100) Nanowire Arrays on a Si(100) Substrate Using an Anodic Aluminum Oxide Template**
TL;DR: In this article, an anodic aluminum oxide (AAO) template with vertical nanopores was used to grow epitaxial Si(100) nanowires on a Si (100) substrate.
Patent
Accumulation field effect microelectronic device and process for the formation thereof
TL;DR: In this article, a gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration.
Journal ArticleDOI
Chemical functionalisation of silicon and germanium nanowires
TL;DR: In this article, the authors explore the strategies available for wet chemical functionalisation of silicon (Si) and germanium (Ge) nanowires and explore the stability and electrical properties of surface modified Si and Ge nanowsires.
Journal ArticleDOI
Origin of Self-Limiting Oxidation of Si Nanowires
H. Cui,C. X. Wang,G. W. Yang +2 more
TL;DR: A new kinetic model is suggested to describe the self-limiting oxidation of Si nanowires by only considering the diffusion step with the influence of stress due to the two-dimension nonuniform deformation of the oxide but not including any rate- Limiting step for interfacial reaction.
Journal ArticleDOI
Self-Limiting Oxidation in Small-Diameter Si Nanowires
TL;DR: In this paper, the formation of ultrasmall diameter core-shell Si-NWs using a dry thermal oxidation of 2 nm diameter (100) Si nanowires at 300 and 1273 K, by means of reactive molecular dynamics simulations using the ReaxFF potential.
References
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Journal ArticleDOI
Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species
TL;DR: The small size and capability of these semiconductor nanowires for sensitive, label-free, real-time detection of a wide range of chemical and biological species could be exploited in array-based screening and in vivo diagnostics.
Journal ArticleDOI
Functional nanoscale electronic devices assembled using silicon nanowire building blocks.
Yi Cui,Charles M. Lieber +1 more
TL;DR: The facile assembly of key electronic device elements from well-defined nanoscale building blocks may represent a step toward a "bottom-up" paradigm for electronics manufacturing.
Journal ArticleDOI
General Relationship for the Thermal Oxidation of Silicon
Bruce E. Deal,A.S. Grove +1 more
TL;DR: In this paper, the thermaloxidation kinetics of silicon are examined in detail based on a simple model of oxidation which takes into account the reactions occurring at the two boundaries of the oxide layer as well as the diffusion process, the general relationship x02+Ax0=B(t+τ) is derived.
Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
High-performance thin-film transistors using semiconductor nanowires and nanoribbons
Xiangfeng Duan,Chunming Niu,Vijendra Sahi,Jian Chen,J. Wallace Parce,Stephen Empedocles,Jay L. Goldman +6 more
TL;DR: It is shown that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process and the approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).