Journal ArticleDOI
Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond
Qiang Huo,Zhenhua Wu,Xingsheng Wang,Weixing Huang,Jiaxin Yao,Jianhui Bu,Feng Zhang,Ling Li,Ming Liu +8 more
TLDR
This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization, which has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.Abstract:
This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization. Seven key device design parameters and their multiple impacts on a 6T SRAM cell are systematically evaluated, focusing on materials band engineering, device design, circuit parameters tradeoff, and variation control. The area of SRAM cell under the same Fin quantization scheme remains constant in all evaluations. To the best of our knowledge, the most comprehensive discussion about circuit optimization from multiple device design parameters perspective is presented. Based on our cooptimization scheme, a SRAM cell is effectively designed. For a low-power and robust SRAM cell design, we achieve 56.7% reduction in leakage, 7.9% improvement in hold noise margin (HNM), 8.6% improvement in read noise margin (RNM), and 10.8% improvement in write margin (WM) at the expense of 19.3% increase in delay under design space of gate length (Lg) and spacer thickness (TSPC). For a high-speed SRAM cell design, we recommend focusing on the optimization of architecture and peripheral circuits. This framework not only has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.read more
Citations
More filters
Journal ArticleDOI
Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors
Weixing Huang,Huilong Zhu,Zhenhua Wu,Xiaogen Yin,Qiang Huo,Kunpeng Jia,Yangyang Li,Yongkui Zhang +7 more
TL;DR: In this paper, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model.
Journal ArticleDOI
Nano Device Simulator—A Practical Subband-BTE Solver for Path-Finding and DTCO
Zlatan Stanojevic,Chen-Ming Tsai,Georg Strof,Ferdinand Mitterbauer,Oskar Baumgartner,C. Kernstock,Markus Karner +6 more
TL;DR: An in-depth discussion on the subband Boltzmann transport methodology, its evolution, and its application to the simulation of nanoscale MOSFETs is presented.
Journal ArticleDOI
Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits
Weixing Huang,Huilong Zhu,Yongkui Zhang,Zhenhua Wu,Kunpeng Jia,Xiaogen Yin,Yangyang Li,Chen Li,Xuezheng Ai,Qiang Huo,Junfeng Li +10 more
TL;DR: A multi-threshold technique was proposed by using NDIBL effect, and it can be manufactured by simple manufacturing process without increasing footprint of transistor.
Journal ArticleDOI
Ternary Logic Circuit Based on Negative Capacitance Field-Effect Transistors and Its Variation Immunity
TL;DR: In this article, a ternary logic inverter based on negative capacitance FETs without additional footprints has been realized, and the third intermediate state can be successfully obtained at ${V}_{\text {DD}}$ /2 in the conventional binary CMOS inverter.
Journal ArticleDOI
Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit
Yanna Luo,Qing-Zhe Zhang,Lei Cao,Weizhuo Gan,Haoqing Xu,Yuliang Cao,Jie Gu,Renren Xu,Gangping Yan,Jiali Huo,Zhenhua Wu,Huaxiang Yin +11 more
TL;DR: In this article , a novel hybrid channel CFET (HC-CFET) is proposed, which takes advantage of the vertical structure and simultaneously co-optimizes the preferred high-electron/holemobility surface of NMOS/PMOS on one substrate.
References
More filters
Journal ArticleDOI
Quantum confinement induced performance enhancement in sub-5-nm lithographic Si nanowire transistors.
TL;DR: This study suggests simple (no additional doping) FETs using tiny top-down nanowires can deliver high performance for potential impact on both CMOS scaling and emerging applications such as biosensing.
Journal ArticleDOI
Experimental study on superior mobility in [110]-oriented UTB SOI pMOSFETs
TL;DR: In this paper, the superior mobility in [110]-oriented ultrathin body (UTB) pMOSFETs with silicon-on-insulator (SOI) thickness (t/sub SOI/) ranging from 32 down to 2.3 nm is experimentally examined for the first time.
Proceedings ArticleDOI
A 7nm CMOS technology platform for mobile and high performance compute application
Shreesh Narasimha,Basanth Jagannathan,A. Ogino,Jaeger Daniel,B. Greene,Christopher D. Sheraw,Kai Zhao,Balasubramanian S. Haran,Unoh Kwon,A. K. M. Mahalingam,B. Kannan,B. Morganfeld,Jessica Dechene,Carl J. Radens,Amanda L. Tessier,A. Hassan,H. Narisetty,I. Ahsan,M. Aminpur,C. An,Michael V. Aquilino,Ankur Arya,Rod Augur,N. Baliga,R. Bhelkar,G. Biery,A. Blauberg,Natalia Borjemscaia,Andres Bryant,Linjun Cao,V. Chauhan,M. Chen,L. Cheng,J. Choo,Cathryn Christiansen,Tao Chu,B. Cohen,R. Coleman,D. Conklin,S. Crown,A. da Silva,Daniel J. Dechene,Garo Jacques Derderian,Sadanand V. Deshpande,Gabriela Dilliway,Keith Donegan,Manfred Eller,Y. Fan,Q. Fang,A. Gassaria,R. Gauthier,Ghosh Somnath,G. Gifford,T. Gordon,M. Gribelyuk,G. Han,J.H. Han,K. Han,M. Hasan,Jack M. Higman,Judson R. Holt,L. Hu,L. Huang,C. Huang,Ting-Hsiang Hung,Y. Jin,Jeyaraj Antony Johnson,Scott C. Johnson,Vivek Joshi,Manoj Joshi,Patrick Justison,S. Kalaga,Tony Tae-Hyoung Kim,W. Kim,Rishikesh Krishnan,Bharat Krishnan,K. Anil,Mahender Kumar,Jae Gon Lee,Rinus T. P. Lee,J. Lemon,S.L. Liew,P. Lindo,M. Lingalugari,M. Lipinski,P. Liu,Jinping Liu,S. Lucarini,W. Ma,E. Maciejewski,S. Madisetti,Arkadiusz Malinowski,Mehta Jaladhi,C. Meng,Souvick Mitra,Christa Montgomery,Hasan M. Nayfeh,T. Nigam,G. Northrop,Katsunori Onishi,Christopher Ordonio,M. Ozbek,Rohit Pal,Sanjay Parihar,O. Patterson,Eswar Ramanathan,I. Ramirez,Rakesh Ranjan,Jeric Sarad,V. Sardesai,S. Saudari,C. Schiller,B. Senapati,C. Serrau,N. Shah,Tian Shen,Haifeng Sheng,Joseph F. Shepard,Y. Shi,Mary Claire Silvestre,Dhruv Singh,Z. Song,J. Sporre,Purushothaman Srinivasan,Z. Sun,Akil K. Sutton,R. Sweeney,Tabakman Keith,M. Tan,Xin Wang,E. Woodard,G. Xu,D. Xu,T. Xuan,Y. Yan,J. Yang,Kong Boon Yeap,M. Yu,A. Zainuddin,Jia Zeng,Kan Zhang,M. Zhao,Y. Zhong,Rick Carter,C-H. Lin,Stephan Grunow,Craig Child,M. Lagus,Robert Fox,E. Kaste,G. Gomba,Srikanth Samavedam,P. Agnello,D. K. Sohn +153 more
TL;DR: A fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization, designed to enable both High Performance Compute (HPC) and mobile applications.
Journal ArticleDOI
Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization
Asen Asenov,Binjie Cheng,Xingsheng Wang,Andrew R. Brown,Campbell Millar,Craig Alexander,Salvatore Maria Amoroso,Jente B. Kuang,Sani R. Nassif +8 more
TL;DR: In this article, the authors used an automated tool flow in a 14 nm CMOS fin-shaped field effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities.
Journal ArticleDOI
Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si 0.45 Ge 0.55 , Ge Gate-All-Around NSFET for 5 nm Technology Node
Jiaxin Yao,Jun Li,Kun Luo,Jiahan Yu,Qingzhu Zhang,Zhaozhao Hou,Jie Gu,Wen Yang,Zhenhua Wu,Huaxiang Yin,Wenwu Wang +10 more
TL;DR: In this paper, a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1− x Ge x -channel gate-all-around nanosheet field effect transistor for 5-nm node is presented.
Related Papers (5)
Implementation of High speed and Low power 6T SRAM cell using FinFET at 22nm technology
A.Sai Kumar,B.S. Priyanka Kumari +1 more