Proceedings ArticleDOI
Potential and limitations of UTBB SOI for advanced CMOS technologies
C. Claeys,Marc Aoulaiche,Eddy Simoen,T. Nicoletti,S. D. dos Santos,Joao Antonio Martino +5 more
- pp 1-6
TLDR
In this paper, the potential of ultra-thin body and buried oxide (UTBB) technologies for digital, analog, and memory applications is discussed, with the focus on low frequency noise and radiation hardness aspects.Abstract:
UTBB (ultra-thin body and ultra-thin buried oxide) technologies are highly competitive for scaled technologies down to the 14 nm range. This paper reviews their potential for digital, analog and memory applications. Attention is also given to low frequency noise and radiation hardness aspects.read more
Citations
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Journal ArticleDOI
Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond
TL;DR: A historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID is provided.
Proceedings ArticleDOI
The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices
C. Claeys,Eddy Simoen,Paula Ghedini Der Agopian,Joao Antonio Martino,Marc Aoulaiche,Bogdan Cretu,Wen Fang,Rita Rooyackers,Anne Vandooren,Anabela Veloso,Malgorzata Jurczak,Nadine Collaert,Aaron Thean +12 more
TL;DR: The influence of new materials, different processing treatments and alternative device concepts on the low frequency noise performance will be reviewed for a variety of advanced device technologies including aspects such as strain engineering, heteroexpitaxial growth, gate-first and gate-last or replacement metal gate integration schemes etc.
Proceedings ArticleDOI
Advanced CMOS Integration Technologies for Future Mobile Applications
C. Claeys,Eddy Simoen +1 more
TL;DR: Several of these different technologies are reviewed and discussed, including III-nitrides, which will play an important role in the RF and power parts of future System-on-Chip applications.
Proceedings ArticleDOI
Challenges for advanced end of the roadmap, beyond Si and beyond CMOS technologies
Cor Claeys,Eddy Simoen +1 more
TL;DR: Design considerations favor the future use of vertical devices like tunnelFETs and nanowires, and attention is also given to the trend and progress in the use of 2D material and devices, spintronics and neuromorphic computing.
References
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Journal ArticleDOI
Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/ƒ) noise
M J Kirton,M J Uren +1 more
TL;DR: In very small electronic devices, the alternate capture and emission of carriers at an individual defect site generates discrete switching in the device resistance, referred to as a random telegraph signal (RTS) as mentioned in this paper.
Journal ArticleDOI
Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study
TL;DR: In this paper, a 3D simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented.
Journal ArticleDOI
Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's
TL;DR: In this article, it has been shown that V/sub th/ fluctuation is mainly caused by the statistical fluctuation of the channel dopant number which explains about 60% of the experimental results.
Proceedings ArticleDOI
Efficient multi-V T FDSOI technology with UTBOX for low power circuit design
C. Fenouillet-Beranger,Olivier P. Thomas,P. Perreau,J.-P. Noel,A. Bajolet,Sebastien Haendler,L. Tosti,Sébastien Barnola,Remi Beneyton,C. Perrot,C. de Buttet,F. Abbate,F. Baron,B. Pernet,Y. Campidelli,L. Pinzelli,Pascal Gouraud,M. Casse,C. Borowiak,Olivier Weber,Francois Andrieu,Konstantin Bourdelle,Bich-Yen Nguyen,F. Boedt,Stephane Denorme,Frederic Boeuf,O. Faynot,Thomas Skotnicki +27 more
TL;DR: For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated and the effectiveness of back biasing for short devices in order to achieve I-ON current improvement by 45% for LVT options at an I-OFF current of 23nA/µm and a leakage reduction by 2 decades.
Proceedings ArticleDOI
Charge pumping SOS-MOS transistor memory
TL;DR: In this article, a new memory cell is proposed, utilizing the inherent features of the floating substrate of SOS-MOS transistors, and the operations of the fabricated cell are also demonstrated.