Journal ArticleDOI
Schottky-Barrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal
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TLDR
An experimental study on Schottky-barrier height tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented in this paper.Abstract:
An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to ~1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV. The process window for the most pronounced SBH modification is dopant dependent.read more
Citations
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Journal ArticleDOI
Considerations for Ultimate CMOS Scaling
TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Journal ArticleDOI
A Comparative Study of Two Different Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height Lowering
TL;DR: In this article, the Schottky barrier height (SBH) of the contact systems of NiSi and PtSi was compared with two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface.
Journal ArticleDOI
Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources
Zhen Zhang,Francois Pagette,Christopher P. D'Emic,Bin Yang,Christian Lavoie,Yu Zhu,Marinus Hopstaken,Siegfried L. Maurer,Conal E. Murray,M. Guillorn,D. Klaus,J.J. Bucchignano,John Bruley,John A. Ott,A. Pyzyna,J. Newbury,W. Song,V Chhabra,G. Zuo,K.-L. Lee,Ahmet S. Ozcan,J. Silverman,Q.C. Ouyang,Dae-Gyu Park,Wilfried Haensch,Paul M. Solomon +25 more
TL;DR: In this article, an extremely low contact resistivity of 6-7 × 10-9 Ω·cm2 between Ni0.9Pt0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation.
Journal ArticleDOI
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs
TL;DR: Using three independent gates, dual-threshold-voltage design is achievable through the use of a wiring scheme on an uncommitted pattern and a range of logic functions is also obtained by replacing VDD and GND by complementary input signals.
Journal ArticleDOI
High- $\kappa$ /Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length
Marwan H. Khater,Zhen Zhang,Jin Cai,Christian Lavoie,Christopher P. D'Emic,Qingyun Yang,Bin Yang,M. Guillorn,D. Klaus,John A. Ott,Yu Zhu,Ying Zhang,Chang Hwan Choi,Martin M. Frank,Kam-Leung Lee,Vijay Narayanan,Dae-Gyu Park,Q.C. Ouyang,Wilfried Haensch +18 more
TL;DR: In this article, the authors demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal.
References
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Journal ArticleDOI
Overview and status of metal S/D Schottky-barrier MOSFET technology
John M. Larson,John P. Snyder +1 more
TL;DR: The metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology as mentioned in this paper offers several benefits that enable scaling to sub-30-nm gate lengths.
Journal ArticleDOI
Metal—Semiconductor Barrier Height Measurement by the Differential Capacitance Method—One Carrier System
TL;DR: In this paper, an expression for the differential capacitance of a metal contact to a semiconductor in which the bulk free carrier density is degenerate or near degenerate is derived.
Proceedings ArticleDOI
Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
TL;DR: In this article, thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm and complementary low-barrier silicides were used to reduce contact and series resistance.
Proceedings ArticleDOI
Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique
TL;DR: In this paper, the dopant segregation (DS) technique is employed and significant modulation of Schottky barrier height is demonstrated, and the DS-SBT fabricated with the current CoSi/sub 2/process show competitive drive current and better short-channel effect immunity compared to the conventional MOSFET.
Journal ArticleDOI
Tuning of NiSi/Si Schottky barrier heights by sulfur segregation during Ni silicidation
TL;DR: The Schottky barrier height (SBH) of NiSi on Si(100) was tuned in a controlled manner by the segregation of sulfur (S) to the silicide∕silicon interface as discussed by the authors.
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