Journal ArticleDOI
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
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TLDR
In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.Abstract:
A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.read more
Citations
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Journal ArticleDOI
MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process
TL;DR: The proposed N(P)MOS-bounded diodes can provide more efficient ESD protection to the internal circuits, as compared to the other diode structures.
Journal ArticleDOI
Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode
TL;DR: In this article, a gate-lifted nMOS electrostatic discharge (ESD) protection device triggered by a p-n-p in series with a diode in a 0.18- $\mu \text{m}$ bulk CMOS technology for 5-V mobile applications up to 85 °C.
Journal ArticleDOI
Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes
Jorge Loayza,Jorge Loayza,Nicolas Guitard,Bruno Allard,Luong Viet Phung,Blaise Jacquier,Philippe Galy +6 more
TL;DR: A new SCR-based device for ESD protection is presented through TCAD simulation and experimental results on a standalone configuration and for a power supply ESD clamp strategy.
Journal ArticleDOI
Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits
Book ChapterDOI
Low-C ESD Protection Design in CMOS Technology
TL;DR: A review on ESD protection designs with low parasitic capacitance for high-frequency applications in CMOS technology is presented in this chapter.
References
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Journal ArticleDOI
The impact of technology scaling on ESD robustness and protection circuit design
A. Amerasekera,C. Duvvury +1 more
TL;DR: In this paper, the trend in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits.
Proceedings ArticleDOI
Dynamic gate coupling of NMOS for efficient output ESD protection
Charvaka Duvvury,Carlos H. Diaz +1 more
TL;DR: In this article, a dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported and the design issues for optimum output ESD protection are also discussed.
Proceedings ArticleDOI
Sub-micron chip ESD protection schemes which avoid avalanching junctions
TL;DR: In this article, an array of ESD protection methods have been developed and tested which depend on forward biased diodes and normal MOSFET conduction, which result in parts made in 0.8 and 0.6 /spl mu/m salicided technologies routinely passing their upper division spec. of /spl plusmn/4500 V HBM without any discernible increase in pin leakage.
Proceedings ArticleDOI
Novel clamp circuits for IC power supply protection
Timothy J. Maloney,S. Dabral +1 more
TL;DR: In this article, the p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps.
Journal ArticleDOI
Internal chip ESD phenomena beyond the protection circuit
TL;DR: In this paper, the issues of protection between V/sub DD/ and V/ sub SS/ are discussed and examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design.
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