Showing papers on "AND gate published in 2000"

Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs

Abstract: Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.

An analytical solution to a double-gate MOSFET with undoped body

Abstract: A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS.

The interpretation and application of Rent's rule

Abstract: This paper provides a review of both Rent's rule and the placement models derived from it. It is proposed that the power-law form of Rent's rule, which predicts the number of terminals required by a group of gates for communication with the rest of the circuit, is a consequence of a statistically homogeneous circuit topology and gate placement. The term "homogeneous" is used to imply that quantities such as the average wire length per gate and the average number of terminals per gate are independent of the position within the circuit. Rent's rule is used to derive a variety of net length distribution models and the approach adopted in this paper is to factor the distribution function into the product of an occupancy probability distribution and a function which represents the number of valid net placement sites. This approach places diverse placement models under a common framework and allows the errors introduced by the modeling process to be isolated and evaluated. Models for both planar and hierarchical gate placement are presented.

Logic-Based Methods for Optimization

Abstract: This paper proposes a logic-based approach to optimization that combines solution methods from mathematical programming and logic programming. From mathematical programming it borrows strategies for exploiting structure that have logic-based analogs. From logic programming it borrows methods for extracting information that are unavailable in a traditional mathematical programming framework. Logic-based methods also provide a unified approach to solving optimization problems with both quantitative and logical constraints.

Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

Abstract: Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.

Method of simulation for gate oxide integrity check on an entire IC

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures of transistor gate oxide. A methodology is provided that is a practical approach to full-chip crosstalk noise verification and gate oxide integrity analysis. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups. Selected signal lines are then fully simulated to determine gate oxide field strengths on transistors connected to the selected signal lines.

Process for forming multiple active lines and gate-all-around MOSFET

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure above active lines manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process. The gate structure can surround more than one side of the active line.

Apparatus and method to characterize the threshold distribution in an NROM virtual ground array

Abstract: A virtual ground array based flash memory device includes a virtual ground array containing individual memory elements with supporting input/output circuitry. Variations occur in the threshold voltage of memory elements contained in the virtual ground array caused by excessive usage of the memory elements. Characterization of the variation of threshold voltage as a function of usage as well as the distribution of the various threshold voltages is important for diagnostic purposes. External sources of voltage and means of determination are necessary to characterize the threshold voltages and the I-V characteristics, when the virtual ground array is in a diagnostic mode. In this mode, the drains, sources, and gates of selected memory elements in the virtual ground array may be under independent external control. The current from the source of the selected memory element is determined in response to the externally controlled voltages, thereby creating an I-V curve. Operational elements contained in input/output multiplexors to the virtual ground array pass externally controlled near ground voltages to the selected memory element. The present arrangement and method of characterizing selected memory elements in the virtual ground array using the source side of the memory elements saves time, conserves power, and is a useful diagnostic tool.

Method of fabricating power rectifier device to vary operating parameters and resulting device

Abstract: A semiconductor rectifying device which emulates the characteristics of a low forward voltage drop Schottky diode and which is capable of a variety of electrical characteristics from less than 1 A to greater than 1000 A current with adjustable breakdown voltage. The manufacturing process provides for uniformity and controllability of operating parameters, high yield, and readily variable device sizes. The device includes a semiconductor body with a guard ring on one surface to define a device region in which are optionally formed a plurality of conductive plugs. Between the guard ring and the conductive plugs are a plurality of source/drain, gate and channel elements which function with the underlying substrate in forming a MOS transistor. The channel regions are defined by using the photoresist mask for the gate oxide with the photoresist mask isotropically etched to expose a peripheral portion of the gate oxide (and gate electrode) with ions thereafter implanted through the exposed gate for forming the channel region. The source/drain (e.g. source) regions can be formed by ion implantation or by out-diffusion from a doped polysilicon layer.

Limits of gate-oxide scaling in nano-transistors

Abstract: This paper explores the ultimate scaling limit of gate oxide due to MOSFET gate leakage and device performance. The limit on Tox reduction with respect to gate leakage tolerance is considered by the concept of "dynamic" gate leakage in nano-scale MOSFET's. Tox scaling is also limited by transistor performance degradation due to the loss of inversion layer charge through gate leakage and the degradation of carrier mobility in the channel from increased scattering. All the three effects are investigated experimentally on CMOS devices with gate length down to 50 nm and gate Tox down to 12 A. The minimum Tox is proposed and the implications on voltage scaling, high-k gate dielectrics and low-temperature CMOS are discussed.

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

Abstract: A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.

Efficient Monte Carlo device modeling

Abstract: A single-particle approach to full-band Monte Carlo device simulation is presented which allows an efficient computation of drain, substrate and gate currents in deep submicron MOSFETs. In this approach, phase-space elements are visited according to the distribution of real electrons. This scheme is well adapted to a test-function evaluation of the drain current, which emphasizes regions with large drift velocities (i.e., in the inversion channel), a substrate current evaluation via the impact ionization generation rate (i.e., in the LDD region with relatively high electron temperature and density) and a computation of the gate current in the dominant direct-tunneling regime caused by relatively cold electrons (i.e., directly under the gate at the source well of the inversion channel). Other important features are an efficient treatment of impurity scattering, a phase-space steplike propagation of the electron allowing to minimize self-scattering, just-before-scattering gathering of statistics, and the use of a frozen electric field obtained from a drift-diffusion simulation. As an example an 0.1-/spl mu/m n-MOSFET is simulated where typically 30 minutes of CPU time are necessary per bias point for practically sufficient accuracy.

All-optical binary counter

Abstract: We experimentally demonstrate an all-optical binary counter composed of four semiconductor optical amplifier based all-optical switching gates The time-of-flight optical circuit operates with bit-differential delays between the exclusive-OR gate used for modulo-2 binary addition and the AND gate used for binary carry detection A movie of the counter operating in real time is presented

High-performance embedded SOI DRAM architecture for the low-power supply

Abstract: This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM.

Optimizing transistor performance in synchronous rectifier buck converters

Abstract: MOSFET performance and gate drive operation play a vital role in efficient power processing. This work studies transistor and gate drive performance in a synchronous rectifier, buck regulator for PC motherboard power management (VRM). The object is to analyze the interaction of the transistors with the drive stage under various operating conditions. Analysis of loss contributions is performed. Emphasis is placed on performance optimization, low cost, and reproducibility.

LCD device driving system and an LCD panel driving method

Abstract: A driving system of an liquid crystal display (LCD) device and an LCD driving method in which an insufficient charging of a liquid crystal capacitor caused by a delayed time taken for raising source and gate signals applied to each pixel of the LCD panel to normal voltage levels is overcome by delaying the source signal output by a predetermined number of source driver IC units or by delaying the gate signal that is output by a predetermined number of gate driver IC units, includes a power supply unit, a controller, a gray voltage generating unit, a gate voltage generating unit, a source drive unit, a gate drive unit, and a liquid crystal panel, wherein the source drive unit or the gate drive unit has a delay unit for delaying an enable signal or a load signal, to thereby output delayed source and gate signals. As a result, a charging rate of the liquid crystal capacitor of pixels contained in the liquid crystal panel is enhanced, which prevents a degradation of the screen and ensures a uniformity achieving a large screen and a high resolution.

Test generation for crosstalk-induced faults: framework and computational results

Abstract: Due to technology scaling and increasing clock frequency, problems due to noise effects are leading to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk-induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times and gate delay. In this paper, we first discuss the general framework of the test generation algorithm followed by computational results. A comparison of our results with SPICE simulations confirms the accuracy of this approach.

Precise test generation for resistive bridging faults of CMOS combinational circuits

Abstract: In this paper we propose a new method to detect resistive bridging faults by logic testing considering fault effects that depend on the gate threshold voltage and gate input vectors. First we show that some bridging faults can be missed to be detected by the traditional test generation method which generates O and 1 at the bridging signal lines, and then propose a novel method to detect resistive bridging faults by logic testing method, which is complete in the sense that the undetectable resistive bridging fault by this algorithm gives correct result in logical operation. A heuristic method using a random pattern has also been proposed for experimental purpose. In order to show the effectiveness of the proposed method some experimental results for benchmark circuits have been shown.

Slope propagation in static timing analysis

Abstract: Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay Therefore, the traditional method for timing analysis may identify the incorrect critical path and report an optimistic delay for the circuit We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods We propose a new timing analysis algorithm which resolves both these issues The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path The algorithm for propagating the corresponding required times is also presented We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional timing analysis method may not We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy Finally, we show how the proposed algorithm was efficiently implemented in an industrial static timing analysis and optimization tool, and present results for a number of industrial circuits Our results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time

Universal-NOT gate

Abstract: The action of a NOT gate on a classical bit results in a change of its value from a 0 to a 1 and vice versa. The action of the classical NOT gate is in principle perfect because with fidelity equal to unity it complements the value of a bit. The action of the quantum NOT gate in a computational basis |0) and |1) is very similar to the action of the classical N()T gate. However, a more general quantum mechanical operation which corresponds to a classical NOT gate would take a qubit in an arbitrary state |Ψ) and produce a qubit in the state |Ψ⊥) orthogonal to |Ψ). This operation is anti-unitary and therefore, cannot be realized exactly. So how well we can do? We find a unitary transformation acting on an input qubit and some auxiliary qubits, which represent degrees of freedom of the quantum NOT gate itself, which approximately realizes the NOT operation on the state of the original qubit. We call this 'device' a universal-NOT gate because the size of the error it produces is independent of the input state. We show that an optimal U-NOT gate which has as its input N identical qubits and produces M outputs achieves a fidelity of F = (N + 1)/ (N + 2), which is equal to the fidelity of estimation of the input qubits. We also show that when a priori information about the state of the input qubit is available, the fidelity of a quantum NOT gate can he much better than the fidelity of estimation.

Transitors with low overlap capacitance

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the gate to drain and gate to source overlap capacitance of deep sub-micron CMOS devices, as an improved means of reducing device switching times. This is accomplished by customizing the gate insulating layer, such that the dielectric constant, K, is lower in the gate to drain and gate to source overlap regions, relative to the more centrally located gate region between the source and drain. This invention avoids the process control problems associated with using conventional post polysilicon gate oxidation as a means of lowering such overlap capacitance, particularly for the deep sub-micron regime.

Self-aligned source and drain extensions fabricated in a damascene contact and gate process

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-k gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Scaling Transistors into the Deep-Submicron Regime

Abstract: The dominant device used in the semiconductor industry today is the silicon-based metal oxide semiconductor (MOS) transistor. The MOS transistor consists of a source, drain, channel, and gate region fabricated in single-crystal silicon (Figure 1). The source region provides a supply of mobile charge when the device is turned “on.” The source is electrically isolated from the drain by the channel region, which is oppositely charged. An insulating oxide layer between the gate and the channel region forms a capacitor. During operation, a voltage is applied to the gate. By applying the appropriate voltage, a conductive layer of charge can be attracted in the channel region at the oxide/silicon interface. This layer of charge acts as a wire that effectively connects the source and drain regions. By changing the voltage on the gate, the conducting layer of charge can be removed. Thus the transistor acts like a switch, with the gate electrode controlling the connection from the source to the drain. These individual switches can be connected to form the basic building blocks for circuit design. These building blocks are used to create the high-performance microprocessors and memory chips in today's computers.

5V compliant transmission gate and the drive logic using 3.3V technology

Abstract: The logic gate has at least one input terminal in which a digital input signal is applied having two possible logical signal values and at least one output terminal to output an output signal having a logical signal values. Two different logical voltage levels are allocated to both possible logical signal values of the output signal and a logic circuit is provided between the input and the output terminals. The logic circuit has several switching elements, especially switching transistors, working or produced according to the logical voltage level. The logic circuit is supplied with a supply potential that exceeds the logic voltage level. The logic circuit has at least two switching elements, especially switching transistors, in the output path allocated to the output terminal.

Noncollinear generation of optical spatiotemporal solitons and application to ultrafast digital logic.

Abstract: We demonstrate theoretically and experimentally that spatiotemporal solitons can be generated through noncollinear second-harmonic generation. The resulting Y geometry could be used to implement an optical AND gate with ultrafast, high-contrast operation but without sensitivity to the phases of the input pulses.

Mix and match: a new approach to secure multiparty computation

Abstract: A method for secure multiparty computation is disclosed In one embodiment, participants to a secure computation agree upon a function to be computed and a representation of the function as a circuit with at least one gate Logical tables are then generated for each gate A logical table includes all possible input and output values for the gate based on the function These input and output values are then encoded and the encoded tables are passed through a mix network, which generates a blinded table for each encoded logical table A blinded table corresponds to the encoded logical table except that its rows are randomly permuted and entries are encrypted After this initial blinding round, participants provide encryptions of their encoded secret inputs The participants then jointly compute the function of interest using the encrypted secret inputs and the representative circuit To simulate a gate therein, the participants compare the encrypted inputs to the gate with each encrypted input entry in the blinded table until a match is detected When a match is detected, the corresponding output entry in the matched row is taken to be the output of the gate This method of mixing and matching is performed in an identical manner for every gate in the circuit, irrespective of the layer in which it resides or the function being computed, until the output of the last gate is identified

Array substrate for use in LCD device

Abstract: A TFT array substrate for use in an LCD device includes at least one repair line to repair line defects. The repair line(s) is formed when forming the pixel electrode so that additional process steps are not required. Accordingly, productivity can be increased. Moreover, either a short-circuit or an open-circuit can be repaired due to the repair line(s). Thus, in the present invention, a TFT array substrate, including: a substrate; a gate line formed on the substrate, arranged in a transverse direction and having a gate electrode; a data line insulated against the gate line by a first insulation layer, arranged in a longitudinal direction perpendicular to the gate line, having a source electrode near the cross point of the gate and data lines, and having first and second data lines which are defined by a cross point of the gate and data lines; a drain electrode space apart from the source electrode over the gate electrode; a pixel electrode connecting to the drain electrode; and a repair line(s) insulated against the data and gate lines by insulation layers and overlapping the gate and data lines, one repair line overlapping a free end of the other repair line and the gate line.

Self-checking Synchronous FSM Network Design with Low Overhead

Abstract: A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-at fault on the FSM poles and gate poles are considered. PLAu realization of FSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLAu realization is derived from the State Transition Graph (STG) description of FSMs with using the m-out-of-n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self-checking one with low overhead is discussed.

Method of manufacturing semiconductor device having nonvolatile memory and logic circuit using multi-layered, inorganic mask

Abstract: An inorganic film with a double-layers structure is used as an etching mask in an EEPROM area to pattern a double-layers gate, while a thin inorganic film obtained by removing one layer of the double-layers inorganic film by etching is used as an etching mask in a CMOS logic circuit area. Therefore, the gate pattern can be formed with high precision by using a thin etching mask in the CMOS logic circuit area.

Power reduction by simultaneous voltage scaling and gate sizing

Abstract: This paper proposes to use voltage-scaling (VS) and gate-sizing (GS) simultaneously for reducing power consumption without violating the timing constraints. We present algorithms for simultaneous VS and GS based on the Maximum-Weighted-Independent-Set problem. We describe the clock distribution of the circuit, completeness of gate library and discreteness of supply voltage, and discuss their effects on power optimization. Experimental results show that the average power reduction ranges from 23.3% to 56.9% over all tested circuits.