Showing papers on "Bandgap voltage reference published in 2014"

A Novel 1.2–V 4.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference

Abstract: This paper proposes a novel CMOS bandgap reference (BGR) with high-order curvature-compensation by using MOS transistors operating in weak inversion region. The mechanism of the proposed curvature-compensation technique is analyzed thoroughly and the corresponding BGR circuit was implemented in standard CMOS 0.18 μm technology. The experimental results show that the proposed BGR achieves 4.5 ppm/°C over the temperature range of -40°C to 120°C at 1.2 V supply voltage. It consumes only 36 μA. In addition, it achieves line regulation performance of 0.054%/V. It is suitable for low-power applications requiring references with high precision.

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit

Abstract: This brief proposes a subthreshold CMOS voltage reference circuit, which reduces the minimum supply voltage by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit, and a digital control circuit. The subthreshold CMOS voltage reference circuit was fabricated using a 0.11-μm CMOS process. Its core area was 0.013 mm 2 and it consumed 5.35 μW at V DD = 250 mV and f CLK = 1 MHz. Its minimum supply voltage was 242 mV. Ten sample chips generated 193-207-mV reference voltage with 0.4-3.2-mV/100-mV line sensitivity at V DD = 250-400 mV and 58-186 ppm/°C temperature coefficient at 10 °C-90 °C.

Reflected wave phenomenon in motor drive systems using wide bandgap devices

Abstract: Fast switching transients from power devices can produce large voltage spikes in motor drive systems with long feeder cable lengths. Referred to as the reflected wave phenomenon, it has been previously demonstrated that the maximum cable length for a given per unit overshoot decreases with increasing switching speed. With the emergence of higher switching speed components based on wide bandgap (WBG) semiconductors, this issue will present itself at shorter feeder cable lengths than comparably rated silicon (Si) devices. This work explores the reflected wave phenomenon for a gallium nitride (GaN) device and compares it to a Si MOSFET. A PSPICE model is created to predict the behavior of this issue. It is validated with experimental results. Tests were performed on a 600 V GaN device, a 600 V Si CoolMOS MOSFET, and a 650 V SiC MOSFET.

A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits

Abstract: This brief provides a novel voltage reference circuit that uses four optimization techniques to effectively save power dissipation: 1) All the amplifiers have been eliminated, but two important voltages are still successfully equalized without using any amplifier; 2) the clock circuits are not required in the proposed design; 3) there is no need for extra biasing circuit; and 4) all the MOS transistors are in the subthreshold region to make the power supply voltage low. Moreover, a trimming circuit has been adopted to ensure the accuracy of the reference voltage. This novel voltage reference circuit has been fabricated with the Semiconductor Manufacturing International Corporation 0.18-μm 1.8-V CMOS process. The measurement results show that the power consumption is only 19 nW, the power supply voltage is only 700 mV, the temperature coefficient is 22.11 ppm/°C under a temperature of -25 °C-+85 °C, and the line sensitivity is as good as 571 μV/V.

Resistorless BJT bias and curvature compensation circuit at 3.4 nW for CMOS bandgap voltage references

Abstract: A novel resistorless bipolar junction transistor (BJT) bias and curvature compensation circuit for ultra-low-power CMOS bandgap voltage references (BGRs) is introduced. It works in the nanoampere current consumption range and under 1 V of power supply. The analytical behaviour of the circuit is described and simulation results for a 0.18 μm CMOS standard process are analysed. A junction voltage of 550 mV at room temperature is obtained (at an emitter current of 3.5 nA), presenting an almost linear temperature dependence, whereas the power consumption of the whole circuit is 3.4 nW under a 0.8 V power supply at 27°C. The estimated silicon area is 0.00135 mm 2 .

Display device and drive current detection method for same

Abstract: A data line drive circuit (120) applies a voltage across a gate-source of a drive transistor (T1) within a pixel circuit (11) according to a voltage for detection and a reference voltage (Vref) and detects a drive current passing through the drive transistor (T1) and being output to the outside of the pixel circuit (11). A threshold voltage correction memory (142) stores data showing a threshold voltage for the drive transistor (T1) for each pixel circuit (11). A display control circuit (100) controls the reference voltage (Vref) on the basis of the data stored in the threshold voltage correction memory (142). Thus, even if the threshold voltage for the drive transistor changes, the drive current can be detected with high precision. The threshold voltage correction memory (142) may store data showing the difference between the threshold voltage for the drive transistor (T1) and the reference voltage (Vref) for each pixel circuit (11).

Ultra-low power and ultra-low voltage bandgap voltage regulator device and method thereof

Abstract: A family of bandgap embodiments are disclosed herein, capable of operating with very low currents and low power supply voltages, using neither any custom devices nor any special manufacturing technology, and fabricated on mainstream standard digital CMOS processes. As such, manufacturing cost can be kept low, manufacturing yields of digital CMOS system-on-a-chip (SOC) that require a reference can be kept optimal, and manufacturing risk can be minimized due to its flexibility with respect to fabrication process node-portability. Although the embodiments disclosed herein use novel techniques to achieve accurate operations with low power and low voltage, this family of bandgaps also uses parasitic bipolar junction transistors (BJT) available in low cost digital CMOS process to generate proportional and complementary to absolute temperature (PTAT and CTAT) voltages via the base-emitter voltage (V EB ) of BJTs and scaling V EB differential pairs to generate the BJTs thermal voltage (V T ).

17.10 0.65V-input-voltage 0.6V-output-voltage 30ppm/°C low-dropout regulator with embedded voltage reference for low-power biomedical systems

Abstract: Supplying a regulated 0.6V to biomedical systems requires a low dropout (LDO) regulator with a maximum driving current capability of 10mA. One sub-1V voltage reference circuit is commonly used in the conventional LDO design to generate the reference voltage VREF with a low temperature coefficient (TC), as shown in Fig. 17.10.1. VREF is sent to the inverting terminal of the error amplifier (EA) to regulate the output voltage VOUT. The critical path of the voltage headroom exists between VREF and VIN through the inverting terminal and the tail current of the EA. That is, VIN>VSG+VOV+VREF ≈|Vtp|+2VOV+VREF, where VIN is the input supply voltage, Vtp is the threshold voltage of the p-type MOSFET and VOV is the overdrive voltage. If the minimum value of VIN is reduced to 0.65V, the derived VREF should be smaller than 50mV when |Vtp| is 0.4V and |VOV| is 0.1V. Such a sub-1V voltage reference circuit is difficult to design [1]-[4]. Even if VREF can be derived, the offset voltage in the EA will seriously affect the exact value of VREF (≤50mV). In addition, the low noise immunity is another disadvantage that severely affects the performance of the biomedical system.

A picopower temperature-compensated, subthreshold CMOS voltage reference

Abstract: A voltage reference consisting of only two nMOS transistors with different threshold voltages is presented. Measurements performed on 23 samples from a single batch show a mean reference voltage of 275.4mV. The subthreshold conduction and the low number of transistors enable to achieve a mean power consumption of only 40pW. The minimum supply voltage is 0.45V, which coincides with the lowest value reported so far. The mean TC in the temperature range from 0 to 120i¾?C is 105.4ppm/i¾?C, while the mean line sensitivity is 0.46%/V in the supply voltage range 0.45-1.8V. The occupied area is 0.018mm2. The power supply rejection rate without any filtering capacitor is -48dB at 20Hz and -29.2dB at 10kHz. Thanks to large area transistors and to a careful layout, the coefficient of variation of the reference voltage is only 0.62%. We introduce as a new figure of merit, the voltage temperature parameter VTP, which gives a direct measure of the overall percentage variation of the reference voltage on the typical 2D domain of supply voltage and temperature. For the proposed circuit, the average VTP is 1.70% with a standard deviation of 0.21%. In order to investigate the effect of transistor area on process variability, a 4X replica of the proposed configuration has been fabricated and tested as well. Except for LS, the 4X replica doesn't exhibit any appreciable improvement with respect to the basic voltage reference. Copyright © 2013 John Wiley & Sons, Ltd.

Single-Event Transient and Total Dose Response of Precision Voltage Reference Circuits Designed in a 90-nm SiGe BiCMOS Technology

Abstract: This paper presents an investigation of the impact of single-event transients (SETs) and total ionization dose (TID) on precision voltage reference circuits designed in a fourth-generation, 90-nm SiGe BiCMOS technology. A first-order uncompensated bandgap reference (BGR) circuit is used to benchmark the SET and TID responses of these voltage reference circuits (VRCs). Based on the first-order BGR radiation response, new circuit-level radiation-hardening-by-design (RHBD) techniques are proposed. An RHBD technique using inverse-mode (IM) transistors is demonstrated in a BGR circuit. In addition, a PIN diode VRC is presented as a potential SET and TID tolerant, circuit-level RHBD alternative.

A −115dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique

Abstract: A novel high PSRR bandgap reference is presented in this paper. Neither operational amplifiers nor any filtering capacitor are used in this design. The circuit employs a self-regulating technique to significantly suppress the supply noise over a broad frequency range. And the problem of supply coupling noise caused by the traditional start-up circuit is also avoided by an improved design. The whole circuit has been implemented in 0.18μm standard CMOS process. Experimental results demonstrate that the PSRR of the voltage reference has achieved -115dB@DC and -90dB@10MHz. A temperature coefficient of 11.68 ppm/°C is obtained in the range of -40°C to 125°C. The current consumption for voltage self-regulating circuit proposed is only 42μA.

High Breakdown Voltage Microelectronic Device Isolation Structure with Improved Reliability

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Reference voltage generator for temperature sensor with trimming capability at two temperatures

Abstract: A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.

Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

Abstract: A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad(Si). The active area of the circuit is about 0.04 mm2.

A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

Abstract: A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in 0.18 ?m standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is 17.6 ppm/oC, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately 0.03 mm2.

Band-gap reference circuit

Abstract: The invention relates to a band-gap reference circuit. The band-gap reference circuit comprises a reference voltage source VREF, a band-gap core circuit, a negative feedback circuit and a starting circuit, wherein gate voltage V_REG is stretched by the reference voltage source VREF so that internal voltage pre-stabilization can be achieved, an internal voltage pre-stabilizing circuit is formed, the band-gap core circuit is provided with an automatic biasing cascode amplifying circuit used for increasing a power supply rejection ratio, the negative feedback circuit provides the supply voltage VDD, processed through voltage stabilization, for the band-gap core circuit, and the starting circuit stretches the reference voltage source VREF when work begins so that the automatic biasing cascode amplifying circuit can work normally. According to the band-gap reference circuit, due to the facts that the supply voltage VDD processed through voltage stabilization is provided for the band-gap core circuit through the negative feedback circuit, and the automatic biasing cascode amplifying circuit is adopted inside for increasing the power supply rejection ratio, area and power consumption are saved.

An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFET

Abstract: An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves medium accuracy (3σ VBG 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm2) that achieve 3σ VBG 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between −40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.

Reference voltage generator

Abstract: Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes: a depletion mode MOS transistor ( 10 ) of a first conductivity type, which is connected to function as a current source and allows a constant current to flow; and an enhancement mode MOS transistor ( 20 ) of the first conductivity type, which has a diode connection, has a mobility substantially equal to a mobility of the depletion mode MOS transistor ( 10 ), and generates a reference voltage (VREF) based on the constant current. The depletion mode NMOS transistor ( 10 ) and the enhancement mode NMOS transistor ( 20 ) have substantially equal mobilities, and thus have substantially equal temperature characteristics so that the temperature characteristics of the reference voltage (VREF) become flat.

A CMOS supply-insensitive with 13ppm/°C temperature coefficient current reference

Abstract: A simple all CMOS low temperature coefficient current reference is designed. Two opposite temperature coefficient supply-insensitive self-bias reference generators that have a function of threshold voltage, mobility and resistor are utilizing to compensate the first-order and second-order temperature curvature. The proposed circuit is designed in AMI 0.5μm process with 5V supply voltage over the temperature range of -45°C to 125 °C. The proposed circuit achieves a 16μA current with temperature coefficient of 13ppm/°C, the supply variation of the designed current is ±1.2% over ±10% VDD change and the accuracy over process variation is ±4.1%.

Compensation circuit for common voltage according to gate voltage

Abstract: Disclosed is a compensation circuit for a common voltage according to a gate voltage, which compensates the common voltage in accordance with variation in gate high voltage, to obtain an optimal common voltage. The compensation circuit includes a divider to divide a gate high voltage, an adder to add a fed-back common voltage to a voltage output from the divider, and a differential amplifier to differentially amplify a voltage output from the adder, and to output the amplified voltage as a compensated common voltage.

A high-order curvature-corrected CMOS bandgap voltage reference with constant current technique

Abstract: A high-order curvature-corrected complementary metal-oxide-semiconductor CMOS bandgap voltage reference BGR, utilizing the temperature-dependent resistor and constant current technique, is presented. Considering the process variation, a resistor trimming network is introduced in this work. The circuit is implemented in a standard 0.35-µm CMOS process. The measurement results have confirmed that the proposed BGR operates with a supply voltage of 1.8 V, consuming 45 µW at room temperature 25 i¾?C, and the temperature coefficient of the output voltage reference is about 5.5 ppm/i¾?C from -40 i¾?C to 125 i¾?C. The measured power supply rejection ratio is -38.8 dB at 1 kHz. The BGR is compatible with low-voltage and low-power circuit design when the structure of operational amplifiers and all the devices in the proposed bandgap reference are properly designed. Copyright © 2012 John Wiley & Sons, Ltd.

0.9 V, 5 nW, 9 ppm/ o C resistorless sub-bandgap voltage reference in 0.18μm CMOS

Abstract: In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/oC for the 0 to 125 °C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 oC. The estimated silicon area is 0.0012 mm2.

Band-gap reference circuit with current compensation

Abstract: The invention discloses a band-gap reference circuit with current compensation The band-gap reference circuit comprises a band-gap reference core circuit, a compensation current generating circuit and a starting circuit According to the reference circuit, on the basis of traditional first-order temperature compensation band-gap references, a current complementary to a first-order temperature compensation voltage curve is generated by the compensation current generating circuit and is converted into a voltage through a resistor R7, and the voltage and a voltage generated by the band-gap reference core circuit are superimposed and summed to generate a high-accuracy output voltage According to the reference circuit, special processes are not required, and high-order compensation can be achieved by adding a small number of MOS tubes and resistors The reference circuit has the advantages of being visual, simple and easy to understand and achieve

2.3 ppm/°c 40 nW MOSFET-only voltage reference

Abstract: A MOSFET-only sub-bandgap voltage reference at less than 50 nW and with very low temperature coefficient is introduced. It consists of a threshold voltage extractor circuit and a proportional to absolute temperature voltage generator, using no resistors. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results for a 0.13 µm CMOS process are presented. It allows a reference voltage below the bandgap, 625 mV in this design example, achieving a temperature coefficient of 2.3 ppm/°C for the -40 to 125 °C temperature range. The circuit consumes 40 nW at 27°C and under 1.2 V supply, being the implemented silicon area 0.0099 mm².

A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control

Abstract: A low-voltage, low-power class-D VCO is presented. An LDO based dynamic supply voltage control technique for the class-D VCO is proposed, which realizes fast and reliable start-up and extremely low-voltage operation of the class-D VCO. The proposed LDO-VCO is fabricated using a 28 nm CMOS technology. The measured phase noise is -115.9 dBc/Hz at 1 MHz offset from the 2.35 GHz carrier, while drawing the current of 760 μA from 0.5 V LDO input. The class-D VCO core consumes 0.171 mW from 225 mV LDO output and the FoM is 191.0 dBc/Hz.

The start-up circuit for a low voltage bandgap reference

Abstract: This paper proposes the startup circuit for a low voltage CMOS bandgap reference circuit. The all MOS scalable voltage bandgap reference (BGR) circuit has been designed and simulated using a standard 65 nm CMOS technology. The proposed startup circuit is simple, smaller in size and uses the feedback mechanism. The BGR circuit provides 661.54 mV of the voltage reference and 9 μA of the current reference with the temperature sensitivity of 4.23 ppm/°C. The total power consumption of the BGR and the startup circuitries are 243 μW and 148 nW respectively.

Demonstration of temperature compensated voltage reference integrated circuit designed with 4H-SiC MESFETs

Abstract: This work demonstrate for the first time a functional high temperature compensated Voltage Reference integrated circuit (IC) on 4H-SiC material, built with MESFET devices. A special finger type MESFET that overcome the typical embedded drain leakage of finger type MESFET, was developed for this purpose. The schematic and the principle of the circuit is based on a new concept design that avoid the bandgap reference topology and the necessity of using an operational amplifier (OpAmp), which is not yet developed on SiC. The experimental temperature coefficient (TC) is significantly better than a Zener diode and comparable to the normal bandgap voltage references on silicon, but the present circuit has the advantage to be able to work beyond 250oC. The circuit contains also a linear temperature sensor.

RF stacked power amplifier bias method

Abstract: The RF stacked power amplifier comprises a voltage-dividing circuit, a negative feedback bias circuit, a current source circuit and a stacked amplifying circuit. The voltage-dividing circuit receives a system voltage and divides the system voltage for outputting a first reference partial voltage and a second reference partial voltage. The negative feedback bias circuit receives a negative feedback reference voltage and correspondingly outputs a second bias reference voltage according to a result of comparing the second reference partial voltage and the negative feedback reference voltage. The current source circuit determines a bias reference current according to the first reference partial voltage. The stacked amplifying circuit outputs the negative feedback reference voltage and determines an operation bias point according to a first bias reference voltage and the bias reference current. The RF stacked power amplifier makes the voltage-drop and the power consumption of each transistor equal via the voltage-dividing circuit.