Showing papers on "Bipolar junction transistor published in 1985"

Resonant tunneling transistor with quantum well base and high‐energy injection: A new negative differential resistance device

Abstract: We propose a new negative conductance device consisting of a heterojunction bipolar transistor with a quantum well and a symmetric double barrier or a superlattice in the base region. The key difference compared to previously studied structures is that resonant tunneling is achieved by high‐energy minority carrier injection into the quantum state rather than by application of an electric field. Thus this novel geometry maintains the crucial, structural symmetry of the double barrier, allowing unity transmission at all resonance peaks and higher peak‐to‐valley ratios and currents compared to conventional resonant tunneling structures. Both tunneling and ballistic injection in the base are considered. These new functional devices have significant potential for a variety of signal processing and multiple‐valued logic applications and for the study of the physics of transport in superlattices.

Two integral relations pertaining to the electron transport through a bipolar transistor with a nonuniform energy gap in the base region

Abstract: The two integral relations by Moll and Ross for the current flow through the base region of a bipolar transistor, and for the base transit time, are generalized to the case of a heterostructure bipolar transistor with a nonuniform energy gap in the base region.

Two-dimensional device simulation program: 2DP

Abstract: Mathematical details of a two-dimensional semiconductor device simulation program are presented, Applicability of the carrier transport model to shallow junction bipolar transistors is discussed. Use of this program to optimize device structures in new bipolar technology is illustrated by presenting calculated device characteristics for variations in a few selected process conditions, Software links that automatically transfer data from a two-dimensional process simulation program and to a quasi-three-dimensional device equivalent circuit model generation program are also discussed.

A unified circuit model for bipolar transistors including quasi-saturation effects

Abstract: This paper describes a compact model for bipolar transistors which includes quasi-saturation effects The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented These equations model both de and charge storage effects Parameter extraction techniques are qualitatively described and the compact model is evaluated using detailed physical simulations of a high voltage bipolar transistor In addition, simulations employing this model are compared with measurements and are found to be in excellent agreement

Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon

Abstract: The hole diffusion length, hole lifetime, hole mobility, and hole equilibrium concentration in epitaxial heavily phosphorus-doped silicon have been measured by a combination of steady-state and transient techniques. Steady state measurements were performed on bipolar transistors in which the base was epitaxially grown. The transient measurement relied on the observation of the decay of the photoluminescence radiation after laser excitation. Significant findings are: 1) the hole mobility is about a factor of two larger in heavily doped n-type silicon than in p-type silicon; 2) the apparent bandgap narrowing is smaller than previously thought, with a value of about 90 meV at a doping level of 1020cm-3.

Super‐gain AlGaAs/GaAs heterojunction bipolar transistors using an emitter edge‐thinning design

Abstract: A novel emitter edge‐thinning structure was adopted for Npn Al0.5Ga0.5As/GaAs single heterojunction bipolar transistors grown by liquid phase epitaxy. In this structure, the emitter edge was etched down to approximately 0.1 μm thick such that the surface and emitter‐base junction depletion regions could touch each other. As a result, the current is blocked from the emitter periphery and the surface leakage current is reduced which improves the current gain especially at low operating current. The best device thus obtained shows a common emitter current gain of 12 500 at a collector current of 50 mA which is the highest gain reported to date for the heterojunction bipolar transistors. The current gain characteristics were indeed improved especially at a collector current below 10 μA.

GaAs bipolar transistors grown on (100) Si substrates by molecular beam epitaxy

Abstract: We have investigated the properties of GaAs homojunction bipolar transistors grown on (100) oriented Si substrates by molecular beam epitaxy. In a structure with a base thickness of 0.2 μm, a small‐signal common emitter current gain β of about 10 at a current density of 10 kA/cm2 has been obtained. Current densities as high as 105 000 A/cm2 were obtained in these devices without degradation demonstrating the excellent stability of this material. Since the minority‐carrier lifetime is quite sensitive to defects in the base region, these measurements demonstrate the high quality of GaAs on Si substrates. From the collector current dependence of current gain, an ideality factor n=1.5 for the emitter junction was obtained, indicating that space‐charge recombination is an important mechanism in these devices. We also demonstrate that the entire GaAs on Si wafer is phase ordered by observing the orientation effect in the mesa etching. These results show that excellent minority‐carrier properties can be obtained...

CMOS voltage references using lateral bipolar transistors

Abstract: Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.

Bipolar - JFET - MOSFET negative resistance devices

Abstract: A systematic method is given for generating negative-resistance circuits made of 2 transistors and linear positive resistors only. The 2 transistors may be bioolar ( n-p-n or p-n-p ), JFET ( n -channel or p-channel), MOSFET ( n -channel or p -channel), or their combinations. Since the circuits do not require an internal power supply, they are passive and can be integrated as a two-terminal device in monolithic form. Two algorithms are given for generating a negative-resistance device which exhibits either a type- N \upsilon - i characteristic similar to that of a tunnel diode, or a type- S \upsilon -i characteristic similar to that of a four-layered p-n-p-n diode. Hundreds of new and potentially useful negative resistance devices have been discovered. A selected catalog of many such prototype negative-resistance devices is included for future applications.

Collector‐emitter offset voltage in AlGaAs/GaAs heterojunction bipolar transistors

Abstract: Factors affecting the collector‐emitter offset voltage in AlGaAs/GaAs heterojunction bipolar transistors have been examined both experimentally and theoretically. In the offset region the collector current, instead of being zero as reported in the literature, is negative and is equal to or less than the base current. The majority of our double heterojunction transistors have negligible offset voltage (50 mV). The prime reason of unusually large offset voltages as observed in some of our devices is found to be the poor quality of the base‐collector (b‐c) junction which is affected by the growth and fabrication processes. The effect of the conduction‐band spike on the offset voltage depends on the compositional grading and in properly graded devices is negligible. For zero offset voltage, high quality of the b‐c junction is important such that its turn‐on voltage is either equal to or higher than that of the emitter‐base junction.

Experimental study of the minority-carrier transport at the polysilicon—monosilicon interface

Abstract: This paper presents the results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contacts. Polysilicon contacts were deposited and heat treated at different conditions. The electrical properties Were measured using p-n junction test structures that are much more sensitive to the contact properties than are bipolar transistors. A simple phenomenological model was used to correlate, the structural properties with electrical measurements. Possible transport mechanisms are examined and estimates are made about upper bounds on transport parameters in the principal regions of the devices. The main conclusion of this study is that the minority-carrier transport in the polycrystalline silicon is dominated by a highly disordered layer at the polysilicon-monosilicon interface characterized by very low minority-carrier mobility. The effective recombination velocity at the n+polysilicon-n+monosilicon interface was found to be a strong function of fabrication conditions. The results indicate that the recombination velocity can be much smaller than 104cm/s.

Semiconductor switch circuit

Abstract: A semiconductor switching device of field-drive type includes a bipolar component having a pnp transistor portion (8) and a npn transistor portion (9), said pnp transistor portion (8) and said npn transistor portion (9) being connected to cause a positive feedback, and a n-channel MOS transistor (11) connected across an emitter electrode (n3) and a collector electrode (n2) of said npn transistor portion (9), wherein a p-channel MOS transistor (10) is connected across an emitter electrode (p1) and a connector electrode (p2) of the pnp transistor portion (8), and a control terminal of said n-channel MOS transistor (11) is electrically connected with a control terminal of said p-channel MOS transistor (10). Said device is operable to control the main drive section even in the floating state and to drive the main drive section by a small control current.

The bipolar inversion channel field-effect transistor (BICFET)—A new field-effect solid-state device: Theory and structures

Abstract: A new solid-state field-effect bipolar device designated the BICFET for bipolar inversion channel field-effect transistor is proposed. The device, which is bipolar in nature and relies upon the field-effect inducement of an inversion layer, that corresponds to the conventional neutral base of a bipolar transistor, features potentially very high current gain (105), very high current operation (106A/cm2) and thus high transconductance (4 × 107S/cm2) and low input capacitance. The BICFET has three terminals: a metallic emitter which makes ohmic contact to a semi-insulator (wide bandgap semiconductor); a source terminal which contacts an inversion layer formed at the interface between the semi-insulator and the semiconductor depletion region; and a collector which is the semiconductor bulk. An important feature of this bipolar device is the absence of the base layer and all of its associated problems. The principle of operation is based on controlling the flow of majority carriers through the semi-insulating region to the collector by the biasing action of charge in the inversion channel. A significant advantage of the BICFET structure is that it is not subject to the scaling limitations due to punchthrough as in the MOS or junction bipolar transistor. The problem of threshold control in the MOS transistor is avoided, so the requirement of very shallow junctions may be relaxed.

A Sensitive Electronic Photoreceptor

Abstract: The photoreceptors in biological systems give meaningful outputs over about six orders of magnitude of illumination intensity. If we are to build an electronic vision system that is truly useful, it must have a similar dynamic range. The elements of an electronic receptor with many orders of magnitude dynamic range are described below. Experimental devices were fabricated in p-well cMOS bulk technology through the MOSIS foundry; npn phototransistors with collector connected to substrate are a byproduct of this process. The n-type bulk forms the collector, the p-well is the base, and the n+ diffusion the emitter. In a typical process, a large transistor of this sort has a current gain β of more than a thousand. Smaller transistors have lower current gains, but are still respectable. The key to very sensitive receptors is to use the current gain of this very clean bipolar transistor before subjecting the signal to any noise from subsequent amplification stages.

Emitter-Base Junction Size Effect on Current Gain Hfe of AlGaAs/GaAs Heterojunction Bipolar Transistors

Abstract: A current gain reduction with emitter-base junction size decrease is found in uniform base AlGaAs/GaAs heterojunction bipolar transistors (HBTs). This characteristic is analyzed using a model that takes into account a lateral diffusion of injected electrons, and is shown to be well explained by this model. The results show the importance of excess base leakage current due to minority carrier recombinations in the external bases of uniform base HBTs.

New formulation of the current and charge relations in bipolar transistor modeling for CACD purposes

Abstract: New, compact analytical formulas for the current and stored charge in a vertical bipolar transistor are derived. The derivation is not based on the charge control concept, but shows how current and charge depend on minority carrier concentrations, which in turn are functions of junction voltages. In this way the influence of the built-in field, the bias-dependent transit times, and the Early effect are incorporated quite naturally. The new set of equations is the framework of a complete transistor model for computer-aided circuit design purposes.

Fabrication methods for high performance lateral bipolar transistors

Abstract: The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

Ion Track Shunt Effects in Multi-Junction Structures

Abstract: Charge collection processes are discussed for heavy ion hits across multiple p-n junctions in bipolar transistor or CMOS structures. The concept of a resistive-like ion track shunt bridging two like conductivity regions is introduced and a first-order-model developed for the charge transported along the ion track shunt. This model is shown to be consistent with charge collection measurements on multi-junction CMOS-like structures. It is found that the charge collection at a given p-n junction is influenced and can even be changed in sign by voltages present at a second p-n junction when the ion track penetrates both junctions. This has important consequences for the design of radiation hard integrated circuits and such ion track shunt effects become more important as device dimensions are scaled to smaller values.

Heavily doped polysilicon-contact solar cells

Abstract: We report the first use of a (silicon)/(heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction or back-surface-field (BSF) structure, of silicon solar cells. Compared with BSF and back-ohmic-contact (BOC) control slimples, the polysilicon-back solar cells, show improvements in red spectral response (RSR) and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Generator for a custom statistical bipolar transistor model

Abstract: An automated model generator (MG) has been developed for a rectangular bipolar device with arbitrary and nonsymmetrical separations of rectangular regions around the emitter perimeter. The MG provides a transistor equivalent circuit whose parameters are determined using a distributed network representing a three-dimensional transistor configuration. The network accounts for nonlinear device dependencies associated with horizontal layout and process technologies. The elements of the distributed network are simple units whose parameters ar derived from measurements or two-dimensional process and device simulations. The MG is versatile and offers several photolithography and processing technology options, with recessed oxide or oxide-nitride defined standard or polysilicon-type base. The resulting lumped-equivalent circuit is used, along with related models of other transistors or device types, for statistical analysis computations of various circuit configurations at different operating temperatures.

Current Induced Avalanche in Epitaxial Structures

Abstract: A correlation is made between observed photoionization induced avalanche breakdown in epitaxial structures and the analysis of high-current effects in these devices using Poisson's equation. The analysis shows that a photocurrent-stimulated conductivity modulation mechanism can lead to avalanche at the epitaxial-substrate junction at bias levels far below the usual breakdown voltages for the structures. Experimental data are presented for both VDMOS power-FET devices and bipolar npn epitaxial transistors which show junction avalanche at low bias levels.

Temperature behavior of insulated gate transistor characteristics

Abstract: The Insulated Gate Transistor (IGT) is a new power semiconductor device with the high input impedance features of the power MOSFET and the ability to operate at high current densities even exceeding that of power bipolar transistors. The high temperature operating characteristics of the device are discussed here. Unlike the power MOSFET whose operating current density decreases by over a factor of 2 when the ambient temperature is raised to 150°C, the IGT is found to maintain its high operating current density at elevated temperatures. The temperature coefficient of the output current is found to be positive at forward drops below 1.5 V and negative at forward drops above 1.5 V. These characteristics make the IGT suitable for applications with high ambient temperatures. The results also indicate that these devices can be paralleled without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.5 V.

Energy-gap reduction in heavily doped silicon: Causes and consequences

Abstract: The authors review briefly the existing theoretical treatments of the various effects that contribute to the reduction of the energy gap in heavily doped Si, namely electron-electron and electron-impurity interactions and the effect of disorder in the impurity distribution. They then turn to the longstanding question why energy-gap reductions extracted from three different types of experiments have persistently produced values with substantial discrepancies, making it impossible to compare with theoretical values. First, they demonstrate that a meaningful comparison between theory and experiment can indeed be made if theoretical calculations are carried out for actual quantities that experiments measure, e.g. luminescence spectra, as recently done by Selloni and Pantelides. Then, they demonstrate that, independent of any theoretical calculations, the optical absorption spectra are fully consistent with the luminescence spectra and that the discrepancies in the energy-gap reductions extracted from the two sets of spectra are caused entirely by the curve-fitting procedures used in analyzing optical-absorption data. Finally, they show explicitly that, as already believed by many authors, energy-gap reductions extracted from electrical measurements on transistors do not correspond to true gap reductions. They identify two corrections that must be added to the values extracted from the electrical data in order to arrive at the true gap reductions and show that the resulting values are in good overall agreement with luminescence and absorption data. They, therefore, demonstrate that the observed reduction in emitter injection efficiency in bipolar transistors is not strictly due to a gap reduction, as generally believed, but to three very different effects.

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

Abstract: Measurements of emitter resistance have been made on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors, fabricated with or without an interfacial oxide layer. It is found that the emitter resistance of phosphorus-doped transistors is considerably lower than that of arsenic-doped transistors. In addition the presence of a deliberately grown interfacial oxide layer leads to a significant increase in emitter resistance for both arsenic- and phosphorus-doped devices.

Lateral insulated gate bipolar transistors with improved latch-up immunity

Abstract: The present invention relates generally to insulated gate transistors and more particularly, to laterally implemented insulated gate transistors having improved current capacity and improved immunity to latch-up. Specifically, it has been found that a lateral insulated gate transistor fabricated on a heavily doped substrate such as a p+ substrate exhibits improved current density. Further, the inclusion of an additional heavily doped region such as a P+ region proximate the base region contributes to improved latch-up immunity within the device.

Current Gain Enhancement in Graded Base AlGaAs/GaAs HBTs Associated with Electron Drift Motion

Abstract: The temperature dependence of current gain in AlGaAs/GaAs heterojunction bipolar transistors with a graded bandgap base (GB-HBTs) is described. High current gain up to 1100 has been achieved at a collector current density of 6?103 A/cm2 in MBE grown GB-HBTs with a 1?1019 cm-3 doped base. The current gain in the low temperature region does not depend on temperature. This tendency is clearly explained by a nearly constant base transit time due to electron drift motion caused by the built-in field, which contrasts with the electron diffusion.

High‐gain, high‐frequency AlGaAs/GaAs graded band‐gap base bipolar transistors with a Be diffusion setback layer in the base

Abstract: AlGaAs/GaAs heterojunction bipolar transistors (HBT’s) with graded band‐gap bases were fabricated from computer‐controlled molecular beam epitaxy layers. It was found that the use of an undoped setback layer of 200–500 A to offset Be diffusion in the emitter resulted in significant current gain increases. Maximum current gains of 1150 for a base width of 0.18 μm were obtained which are the highest yet reported for graded base HBT’s. Zn diffusion was used to contact the base and provides a low base contact resistance. Microwave s‐parameter measurements yielded fT=5 GHz and fmax=2.5 GHz. Large signal pulse measurements resulted in rise times of τr∼150 ps and pulsed collector currents of Ic>100 mA which is useful for high current laser drivers.

NpnN double-heterojunction bipolar transistor on InGaAsP/InP

Abstract: Double‐heterojunction bipolar transistors have been fabricated on InGaAs(P)/InP with current gains of up to 200. Transistors with a p+‐InGaAs/N‐InP base/collector junction exhibited drastic gain reduction at low collector bias voltages which is ascribed to the electron repelling effect of the conduction‐band spike formed at the collector heterojunction. To overcome this complication a thin n‐InGaAs transition layer was inserted between the ternary base and the InP wide‐gap collector. The resulting nN double‐layer collector structure leads to excellent current/voltage characteristics.

A new superconducting-base transistor

Abstract: The continuing search for a good cryogenic transistor has led to a new proposal, the superconducting-base semiconductor-isolated transistor (SUB-SIT). This three-terminal device is expected to have characteristics very similar to those of bipolar transistors, but at millivolt operating levels. We present discussions of the concepts involved in the SUBSIT, proposed fabrication techniques, and theoretical results for its DC and high frequency characteristics.

An amorphous SiC:H emitter heterojunction bipolar transistor

Abstract: After confirming the successful application of the amorphous SiC:H(a-SiC:H)/crystalline Si(c-Si) heterostructure in a solar cell and considering its prospective application in Bi-CMOS devices, an attempt has been made to apply the same in the fabrication of a heterojunction bipolar transistor. A p-n-p heterojunction bipolar transistor with a wide band-gap boron-doped amorphous SiC:H emitter and crystalline Si (base, collector) has been realized and is reported here for the first time. Good device performance has been observed at the a-SiC:H deposition temperature of 450°C. Preliminary results gave a current gain, h_{FE(\max)} ) of 50 at a current density of approximately 2.4 A/cm2(base dose 2 × 1012/cm2, width ≃ 0.4 µm). Temperature dependence of the transistor h_{FE}-I_{C} characteristics was also studied.