Showing papers on "Bipolar junction transistor published in 1989"

The Monte Carlo Method for Semiconductor Device Simulation

Abstract: 1 Introduction.- References.- 2 Charge Transport in Semiconductors.- 2.1 Electron Dynamics.- 2.2 Energy Bands.- 2.2.1 Relationship of Energy to Wavevector.- 2.2.2 Effective Masses.- 2.2.3 Nonparabolicity.- 2.2.4 Herring and Vogt Transformation.- 2.2.5 Actual Bands of Real Semiconductors.- 2.3 Scattering Mechanisms.- 2.3.1 Classification and Physical Discussion.- 2.3.2 Fundamentals of Scattering.- 2.4 Scattering Probabilities.- 2.4.1 Phonon Scattering, Deformation-Potential Interaction.- 2.4.2 Phonon Scattering, Electrostatic Interaction.- 2.4.3 Ionized Impurity Scattering.- 2.4.4 Carrier-Carrier Scattering.- 2.5 Transport Equation.- 2.6 Linear Response and the Relaxation Time Approximation.- 2.6.1 Relaxation Times for the Various Scattering Mechanisms.- 2.6.2 Carrier Mobilities in Various Materials.- 2.7 Diffusion, Noise, and Velocity Autocorrelation Function.- 2.7.1 Basic Macroscopic Equations of Diffusion.- 2.7.2 Diffusion, Autocorrelation Function, and Noise.- 2.7.3 Electron Lifetime and Diffusion Length.- 2.8 Hot Electrons.- 2.9 Transient Transport.- 2.10 The Two-dimensional Electron Gas.- 2.10.1 Subband Levels and Wavefunctions.- 2.10.2 Scattering Rates.- References.- 3 The Monte Carlo Simulation.- 3.1 Fundamentals.- 3.2 Definition of the Physical System.- 3.3 Initial Conditions.- 3.4 The Free Flight, Self Scattering.- 3.5 The Scattering Process.- 3.6 The Choice of the State After Scattering.- 3.6.1 Phonon Scattering, Deformation-Potential Interaction.- 3.6.2 Phonon Scattering, Electrostatic Interaction.- 3.6.3 Ionized Impurity Scattering.- 3.6.4 Carrier-Carrier Scattering.- 3.7 Collection of Results for Steady-State Phenomena.- 3.7.1 Time Averages.- 3.7.2 Synchronous Ensemble.- 3.7.3 Statistical Uncertainty.- 3.8 The Ensemble Monte Carlo (EMC).- 3.9 Many Particle Effects.- 3.9.1 Carrier-Carrier Scattering.- 3.9.2 Molecular Dynamics and Monte Carlo Method.- 3.9.3 Degeneracy in Monte Carlo Calculations.- 3.10 Monte Carlo Simulation of the 2DEG.- 3.11 Special Topics.- 3.11.1 Periodic Fields.- 3.11.2 Diffusion, Autocorrelation Function, and Noise.- 3.11.3 Ohmic Mobility.- 3.11.4 Impact Ionization.- 3.11.5 Magnetic Fields.- 3.11.6 Optical Excitation.- 3.11.7 Quantum Mechanical Corrections.- 3.12 Variance-reducing Techniques.- 3.12.1 Variance Due to Thermal Fluctuations.- 3.12.2 Variance Due to Valley Repopulation.- 3.12.3 Variance Related to Improbable Electron States.- 3.13 Comparison with Other Techniques.- 3.13.1 Analytical Techniques.- 3.13.2 The Iterative Technique.- 3.13.3 Comparison of the Different Techniques.- References.- 4 Review of Semiconductor Devices.- 4.1 Introduction.- 4.2 Historical Evolution of Semiconductor Devices.- 4.2.1 Evolution of Si Devices.- 4.2.2 Evolution of GaAs Devices.- 4.2.3 Technological Features.- 4.2.4 Scaling and Miniaturization.- 4.3 Physical Basis of Semiconductor Devices.- 4.3.1 p-n Junction.- 4.3.2 Bipolar Transistors.- 4.3.3 Heterojunction Bipolar Transistor.- 4.3.4 Metal-Semiconductor Contacts.- 4.3.5 Metal-Semiconductor Field-Effect Transistor.- 4.3.6 Metal-Oxide-Semiconductor Field-Effect Transistor.- 4.3.7 High Electron Mobility Transistor.- 4.3.8 Hot Electron Transistors.- 4.3.9 Permeable Base Transistor.- 4.4 Comparison of Semiconductor Devices.- 4.4.1 Device Parameters.- 4.4.2 Comparison of Semiconductor Devices.- References.- 5 Monte Carlo Simulation of Semiconductor Devices.- 5.1 Introduction.- 5.2 Geometry of the System.- 5.2.1 Boundary Conditions.- 5.2.2 Grid Definition.- 5.2.3 Superparticles.- 5.3 Particle-Mesh Force Calculation.- 5.3.1 Particle-Mesh Calculation in One Dimension.- 5.3.2 Charge Assignment Schemes in Two Dimensions.- 5.4 Poisson Solver and Field Distribution.- 5.4.1 Finite Difference Scheme.- 5.4.2 Matrix Methods.- 5.4.3 Rapid Elliptic Solvers (RES).- 5.4.4 Iterative Methods.- 5.4.5 Calculation of the Electric Field.- 5.4.6 The Collocation Method.- 5.5 The Monte Carlo Simulation of Semiconductor Devices.- 5.5.1 Initial Conditions.- 5.5.2 Time Cycles.- 5.5.3 Free Flight.- 5.5.4 Scattering.- 5.5.5 Carrier-Carrier Scattering.- 5.5.6 Degenerate Statistics.- 5.5.7 Statistics.- 5.5.8 Static Characteristics.- 5.5.9 A.C. Characteristics.- 5.5.10 Noise.- References.- 6 Applications.- 6.1 Introduction.- 6.2 Diodes.- 6.2.1 n+-n-n+ Diodes.- 6.2.2 Schottky Diode.- 6.3 MESFET.- 6.3.1 Short Channel Effects.- 6.3.2 Geometry Effects.- 6.3.3 Space-Charge Injection FET.- 6.3.4 Conclusions.- 6.4 HEMT and Heterojunction Real Space Transfer Devices.- 6.4.1 HEMT.- 6.4.2 Real-Space Transfer Devices.- 6.4.3 Velocity-Modulation Field Effect Transistor.- 6.5 Bipolar Transistor.- 6.6 HBT.- 6.7 MOSFET and MISFET.- 6.7.1 MOSFET.- 6.7.2 GaAs Injection-modulated MISFET.- 6.7.3 Conclusions.- 6.8 Hot Electron Transistors.- 6.8.1 The THETA Device.- 6.8.2 GaAs FET with Hot-Electron Injection Structure.- 6.8.3 Planar-doped-Barrier Transistors.- 6.9 Permeable Base Transistor.- 6.10 Comparison with Traditional Simulators.- References.- Appendix A. Numerical Evaluation of Some Integrals of Interest.- References.- Appendix B. Generation of Random Numbers.- References.

Semiconductor Device Modeling with Spice

Abstract: From the Publisher: With all the clarity and hands-on practicality of the best-selling first edition,this revised version explains the ins and outs of SPICE,plus gives new data on modeling advanced devices such as MESFETs,ISFETs,and thyristors. And because it's the only book that describes the models themselves,it helps readers gain maximum value from SPICE,rather than just telling them how to run the program. This guide is also distinctive in covering both MOS and FET models. Step by step,it takes the reader through the modeling process,providing complete information on a variety of semiconductor devices for designing specific circuit applications. These include: Pn junction and Schottky diodes; bipolar junction transistor (BJT); junction field effect transistor (JFET); metal oxide semiconductor transistor (MOST); metal semiconductor field effect transistor (MESFET); ion sensitive field effect transistor (ISFET); semiconductor controlled rectifier (SCR-thyristor).

Heterojunction bipolar transistors using Si-Ge alloys

Abstract: Advanced epitaxial growth techniques permit the use of pseudomorphic Si/sub 1-x/Ge/sub x/ alloys in silicon technology. The smaller bandgap of these alloys allows for a variety of novel band-engineered structures that promise to enhance silicon-based technology significantly. The authors discuss the growth and properties of pseudomorphic Si/sub 1-x/Ge/sub x/ structures and then focus on their applications, especially the Si/sub 1-x/Ge/sub x/-base heterojunction bipolar transistor (HBT). They show that HBTs in the Si/sub 1-x/Ge/sub x/ system allow for the decoupling of current gain and intrinsic base resistance. Such devices can be made by using a variety of techniques, including molecular-beam epitaxy and chemical vapor deposition. The authors describe the evolution of fabrication schemes for such HBTs and describe the DC and AC results obtained. They show that optimally designed HBTs coupled with advanced bipolar structures can provide performance leverage. >

Quantum functional devices: resonant-tunneling transistors, circuits with reduced complexity, and multiple valued logic

Abstract: Recent advances in the area of quantum functional devices are discussed. After a discussion of the functional device concept, resonant-tunneling bipolar transistors (RTBTs) with a double barrier in the base region are described. Design considerations for RTBTs with ballistic injection and the first observation of minority-electron ballistic RT are presented. RTBTs using thermionic injection and exhibiting a high peak-to-valley ratio at room temperature in the transfer characteristics are also described. Multiple-state RTBTs and their DC and microwave performance are then discussed. Circuit applications of RTBTs also are discussed. It is shown that RTBTs allow the implementation of many analog and digital circuit functions with a greatly reduced number of transistors and show considerable promise for multiple-valued logic. Experimental results on frequency multipliers and parity bit generators are presented. Analog-to-digital converters are memory circuits are also discussed. Two novel superlattice-base transistors are reported. Negative transconductance is achieved by suppression of injection into minibands. Gated quantum-well RT transistors are also discussed. >

Subpicosecond InP/InGaAs heterostructure bipolar transistors

Abstract: Bipolar transistors with subpicosecond extrinsic delay are discussed. These InP/InGaAs heterostructure transistors show a unity-current-gain cutoff frequency f/sub $/T=165 GHz and maximum oscillation frequency f/sub MAX/=100 GHz at room temperature. The authors model shows that an f/sub $/T beyond 386 GHz is obtainable by further vertical scaling. Ring oscillators implemented with nonthreshold logic (NTL) and transistors having f/sub MAX/=71 GHz show a propagation delay of 14.7 ps and 5.4 mW average power consumption per stage. >

GaAlAs/GaAs heterojunction bipolar transistors: issues and prospects for application

Abstract: Issues important for the manufacturing of GaAlAs/GaAs heterojunction bipolar transistors (HBTs) and their prospects for application in various areas are discussed. The microwave and digital performance status of HBTs is reviewed. Extrapolated values of maximum frequency of oscillation above 200 GHz and frequency divider operation at 26.9 GHz are reported. Key prospects for further device development are highlighted. >

Bandgap and transport properties of Si/sub 1-x/Ge/sub x/ by analysis of nearly ideal Si/Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors

Abstract: Si/Si/sub 1-x/Ge/sub x//Si N-p-N heterojunction bipolar transistors (HBTs) produced by a chemical vapor deposition technique, limited-reaction processing, were analyzed using electrical measurements to determine properties of strained Si/sub 1-x/Ge/sub x/. The band discontinuities between Si and strained Si/sub 1-x/Ge/sub x/ were found by measuring the collector and base currents as a function of temperature. The electron diffusion coefficient in p-type Si/sub 1-x/Ge/sub x/ was extracted by measuring the change in collector current with Si/sub 1-x/Ge/sub x/ base width. The electron diffusion coefficient perpendicular to the heterointerface in the strained Si/sub 1-x/Ge/sub x/ layers studied here is smaller than that in Si doped to the same level. The reverse leakage currents at the base-emitter junction of the HBTs are smaller than the leakage at the collector-base junction, but in Si control transistors the situation is reversed. The high leakage currents at the collector-base junction in the HBTs are believed to result from the preferred accumulation of misfit dislocations at the strained interface closest to the substrate. >

An improved understanding for the transient operation of the power insulated gate bipolar transistor (IGBT)

Abstract: It is shown that a nonquasi-static analysis must be used to describe the transient current and voltage waveforms of the IGBT (insulated-gate bipolar transistor). The nonquasi-static analysis is necessary because the transports of electrons and holes are coupled for the low-gain, high-level injection conditions, and because the quasi-neutral base width changes faster than the base transit speed for typical load circuit conditions. To verify that both of these nonquasi-static effects must be included, the predictions of the quasi-static and nonquasi-static models are compared with measured current and voltage switching waveforms. The comparisons are performed for different load circuit conditions and for different device base lifetimes. >

Thermal design studies of high-power heterojunction bipolar transistors

Abstract: A theoretical thermoelectro-feedback model has been developed for the thermal design of high-power GaAlAs/GaAs heterojunction bipolar transistors (HBTs). The power-handling capability, thermal instability, junction temperature, and current distributions of HBTs with multiple emitter fingers have been numerically studied. The calculated results indicate that power HBTs on Si substrates (or with Si as the collector) have excellent potential power performance and reliability. The power-handling capability on Si is 3.5 and 2.7 times as large as that on GaAs and InP substrates, respectively. The peak junction temperature and temperature difference on the chip decrease in comparison to the commonly used Si homostructure power transistor with the same geometry and power dissipation. Thereby HBTs are promising for high-speed microwave and millimeter-wave applications. It has been also found that the nonuniform distribution of junction temperature and current can be greatly improved by a ballasting technique that uses unequal-valued emitter resistors. >

Band lineup for a GaInP/GaAs heterojunction measured by a high‐gain Npn heterojunction bipolar transistor grown by metalorganic chemical vapor deposition

Abstract: A GaInP(N)/GaAs( p) heterojunction bipolar transistor was fabricated by metalorganic chemical vapor deposition (MOCVD) for the first time. The common‐emitter current gain exceeded 200 at a current density around 10 A/cm2 and the offset voltage was as small as 50 mV. Thermionic emission theory indicates that the conduction‐band discontinuity (ΔEc) at GaInP/GaAs heterointerface is as small as 30 meV at room temperature and this value was more than 160 meV smaller than 0.19–0.22 eV obtained by the C‐V profile method. The band‐gap energy for MOCVD‐grown GaInP was 60 meV smaller than the intrinsic band‐gap energy (1.91 eV), but this value is too small to explain the difference between the present ΔEc value and the previously reported ΔEc value.

GaAs heterojunction bipolar transistor device and IC technology for high-performance analog and microwave applications

Abstract: GaAs-AlGaAs n-p-n heterojunction bipolar transistor (GaAs HBT) technology and its application to analog and microwave functions for high-performance military and commercial systems are discussed. In many applications the GaAs HBT offers key advantages over the alternative advanced silicon bipolar and III-V compound field-effect-transistor (FET) approaches. TRW's GaAs HBT device and IC fabrication process, basic HBT DC and RF performance, examples of applications, and technology qualification work are presented and serve as a basis for addressing general capability issues. A related 3- mu m emitter-up, self-aligned HBT IC process provides excellent DC and RF performance, with simultaneous gain-bandwidth product, f/sub T/, and maximum frequency of oscillation, f/sub max/, of approximately 20-40 GHz and DC current gain beta approximately=50-100 at useful collector current densities approximately=3-10 kA/cm/sup 2/, early voltage approximately=500-1000 V, and MSI-LSI integration levels. These capabilities facilitate versatile DC-20-GHz analog/microwave as well as 3-6 Gb/s digital applications, 2-3 G sample/s A/D conversion, and single-chip multifunctions with producibility. >

Realization of a three-terminal resonant tunneling device: The bipolar quantum resonant tunneling transistor

Abstract: A new three‐terminal resonant tunneling structure in which current transport is controlled by directly modulating the potential of the quantum well is proposed and demonstrated Typical current gains of 50 at room temperature are observed

Collector-base junction avalanche effects in advanced double-poly self-aligned bipolar transistors

Abstract: Observation of base-current reversal induced by avalanche multiplication is reported in advanced self-aligned bipolar devices at a collector junction reverse bias less than 3 V. Temperature measurements were carried out to verify the avalanche mechanism, and the dependence on the collector doping profile and high-level injection effects was investigated both experimentally and by numerical simulations. The avalanche effect, which is expected to aggravate with scaling, will eventually threaten normal circuit operation if certain criteria for base-collector reverse bias cannot be maintained. >

Analysis of the operation of GaAlAs/GaAs HBTs

Abstract: Drift-diffusion modeling in two dimensions has been used to characterize and analyze storage, transport and recombination effects in GaAlAs/GaAs heterostructure bipolar transistors Both intrinsic and parasitic effects have been studied, and their relationship to the design of the device is discussed For conventional dopings and high current densities, the heterojunction grading potential causes a barrier in the base-emitter junction, which results in a large increase in the dynamic resistance In heterojunction collectors, a similar barrier leads to a large increase in base charge storage and to spreading of the collector current It is shown that increased doping levels can successfully suppress these barrier effects The capacitance and transport phenomena at the base-emitter junction are also analyzed under conditions of large forward bias, where the junction space-charge region is shorter than the alloy grading length Recombination is analyzed in the limit of high surface recombination velocities using Shockley-Read-Hall theory in the presence of Fermi-level pinning due to surface states The pinning results in a potential energy saddle point at the edge of the base-emitter junction, which largely determines the surface recombination behavior of the transistor when the recombination velocity is high >

500-V n-channel insulated-gate bipolar transistor with a trench gate structure

Abstract: An improved insulated-gate bipolar transistor (IGBT) with a trench gate structure that demonstrates a low forward voltage drop of 1.2 V at a forward conduction current density of 200 A/cm/sup 2/ is described. This device structure was fabricated using a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 6 mu m. This allows for a fivefold increase of channel density and elimination of the parasitic JFET effect, thus reducing the forward voltage drop significantly. A static latching current density of 2700 A/cm/sup 2/ has been achieved in the UMOS-IGBT. Two-dimensional computer simulations of the UMOS-IGBT have been performed to identify the optimal cell design. This optimal design is predicted to increase the SOA current density by a factor of 2.9 over the state-of-the-art DMOS-IGBT. >

A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS

Abstract: A variable-gain amplifier (VGA) with a gain range of 50 dB has been implemented in a standard 3 mu m CMOS process using parasitic lateral and vertical bipolar transistors to form the core of the circuit. The bipolar transistors had been characterized extensively. The VGA has a bandwidth larger than 3 MHz over the whole gain range and operates on a single 5 V power supply. The active area is about 0.8*0.9 mm/sup 2/. >

Graded-SiGe-base, poly-emitter heterojunction bipolar transistors

Abstract: Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors (HBTs) fabricated using a low-temperature epitaxial technique to form the SiGe graded-bandgap base layer are discussed. These devices were fabricated on patterned substrates and subjected to annealing cycles used in advanced bipolar processing. These devices, which have base widths under 75 mm, were found to have excellent junction qualities. Due to the small bandgap of SiGe, the collector current at low bias is ten times higher than that for Si-base devices that have a pinched base resistance. This collector current ratio increases to more than 40 at LN/sub 2/ temperature resulting in current gains of 1600 for the SiGe-base transistors despite base sheet resistances as low as 7.5 k Omega / Square Operator . >

Influence of device parameters on the switching speed of BiCMOS buffers

Abstract: The influence of different MOS and bipolar device parameters on the switching speed of a BiCMOS buffer is described. This influence is studied by looking at the response of a BiCMOS inverter to a step input. Using suitable approximations for the high-level injection effects in the bipolar transistor, mathematical approximations for the response are derived. The approximate responses are compared to those determined by SPICE simulations and the agreement is satisfactory. High-current effects in the bipolar transistor strongly affect the performance. The effects of different bipolar transistor parasitic resistors are investigated, and it is found that only the collector resistance is important. The influence of different emitter sizes on the delay time is studied, and it is shown that for a given area, there is one optimal size ratio for the MOS and bipolar transistors for which the delay is minimum. >

Hot-electron InGaAs/InP heterostructure bipolar transistors with f/sub T/ of 110 GHz

Abstract: A hot-electron InGaAs/InP heterostructure bipolar transistor (HBT) is discussed. A unity-current-gain cutoff frequency of 110 GHz and a maximum frequency of oscillation of 58 GHz are realized in transistors with 3.2*3.2- mu m/sup 2/ emitter size. Nonequilibrium electron transport, with an average electron velocity approaching 4*10/sup 7/ cm/s through the thin (650 AA) heavily doped (p=5*10/sup 19/ cm/sup -3/) InGaAs base and 3000-AA-wide collector space-charge region, results in a transit delay of 0.5 ps corresponding to an intrinsic cutoff frequency of 318 GHz. >

Merged bipolar and insulated gate transistors

Abstract: A vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistor is formed in and along one of the sidewalls of the structure. Source and drain regions are formed in the structure by ion-implantation using a polysilicon gate electrode formed over a gate insulator on the sidewall as a self-aligning mask.

Submicron integrated circuits

Abstract: The submicrometer silicon MODFET scaling the silicon bipolar transistor submicron gaas, AlGaAs/GaAs, and AlGaAs/InGaAs transistors ultrahigh-speed HEMT LSI circuits resonant tunneling devices and their applications electrical modeling interconnections impact of VLSI technology scaling on computer architectures lateral surfacr superlattices two-dimensional automata in VLSI VLSI electronic neural networks rapid thermal processing of silicon lithography.

On the low-temperature static and dynamic properties of high-performance silicon bipolar transistors

Abstract: In a study performed over the temperature range of 400 to 77 K, Si bipolar transistors were found to have near-ideal characteristics at low temperatures with beta as high as 80 at 77 K. Detailed calculations indicate that the conventional theory of the temperature dependence of beta does not match the data. The discrepancy can be removed if it is assumed that a phenomenological thermal barrier to hole injection is present. Emitter-coupled logic (ECL) ring oscillators are functional at 85 K with no degradation in speed until about 165 K when compared to 358 K (85 degrees C). Calculations using a delay figure of merit indicate that f/sub T/, R/sub b/, and C/sub c/ are the delay components most affected by low-temperature operation. The feasibility of reduced logic swing operation of bipolar circuits at low temperatures is examined. It is found that successful ECL circuit operation at reduced logic swings is possible provided emitter resistance is kept small and can be used to enhance low-temperature power-delay performance. These data suggest that conventionally designed high-performance bipolar devices are suitable for the low-temperature environment. >

Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

Ultrahigh Be doping of Ga0.47In0.53As by low‐temperature molecular beam epitaxy

Abstract: Layers of Ga0.47In0.53As grown on InP by a beam epitaxy method have been doped with Be to p=5×1020 cm−3 by growth at substrate temperatures as low as 365 °C. The maximum doping level is strongly growth temperature dependent. Heterostructure bipolar transistors with base doping p=1×1020 cm−3, current gain β=54, and unity current gain cutoff frequency fT=140 GHz are illustrated.

Model for CMOS/SOI single-event vulnerability

Abstract: A lumped-parameter model derived from transistor characterization data has been used in SPICE analyses to study and predict the single-event-upset thresholds for SIMOX SOI (separation by implantation of oxygen, silicon-on-insulator) SRAMs (static random-access memories) with a variety of cell designs. The modeling of CMOS/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure. Results indicate that, in the SOI devices investigated, single events simulate a localized bipolar response, even in devices with bodies electrically tied to active nodes. The bipolar response enhances the destabilizing effect of an ion event. The total current impulse contributing to upset can be significantly greater than that produced by direct ionization within the hit transistor, i.e., devices can be upset by ions that deposit less than the total charge required to initiate logic state reversal. In light of this, advanced CMOS/SOI-SOS logic with short channel lengths (and therefore significant parasitic bipolar gain) may exhibit critical LETs (linear energy transfers) lower than expected from simple scaling rules, and thinning of the active regions may not significantly reduce single-event rates in such CMOS/SOI digital circuits. >

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

Abstract: A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector. >

Small-geometry, high-performance, Si-Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors

Abstract: Si-Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors (HBTs) with very heavily doped bases, fabricated using electron-beam lithography to obtain very small feature sizes, are discussed. Emitter, base, and collector epitaxial layers were grown in situ in a lamp-heated, chemical-vapor-deposition reactor. Transistors with common-emitter current gain of approximately 50 and f/sub t/ of about 28 GHz have been obtained. Analysis indicates that the frequency response is limited by parasitic resistances and capacitances in the simple demonstration structure used, rather than by the intrinsic device characteristics. Simple ring oscillators have been fabricated using HBTs in the inverse-active mode of operation. >

Future BiCMOS technology for scaled supply voltage

Abstract: A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar transistor structure BEST and in the CBiCMOS and BiNMOS gate circuit configuration are highly promising in comparison to CMOS ULSIs for future high-speed and high-density ULSIs operating at scaled supply voltages. >

A new recombination model describing heavy-doping effects and low-temperature behaviour

Abstract: Measurements on the reverse and nonideal forward currents in heavily doped diodes and in advanced bipolar transistors in the temperature range from 77 K to 300 K are presented. A detailed comparison is made between these measurements and various models. It is shown that models from the literature fail to describe all observed phenomena. A model is proposed which is shown to provide a good description of the measured heavy-doping effects on recombination. The model describes the experimentally observed voltage and temperature dependence of both the nonideal forward and the reverse currents without the introduction of fitting parameters. It is shown that, for zero-bias depletion widths between 300 AA and about 700 AA, trap-assisted tunneling is important for reverse-biased junctions at room temperature. For zero-bias depletion widths less than 300 AA, the tunneling effects increase dramatically. Whereas trap-assisted tunneling has to be taken into account for the forward characteristic, the reverse characteristic is dominated by band-to-band tunneling. >

Application of insulated gate bipolar transistor to zero-current switching converters

Abstract: The problems associated with insulated-gate bipolar transistor (IGBT) devices in PWM converters, such as turn-off current tailing and turn-off latching, are largely avoided in zero-current switching resonant converters. Phenomena induced by dv/dt, such as the power losses and latching, are identified as the predominant problems in using IGBT devices for very-high-frequency resonant operations. The discussion and the verification of the results presented are focused on buck-type converters in the zero-current switching family. >