Showing papers on "CMOS published in 1994"

Power consumption estimation in CMOS VLSI chips

Abstract: Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15%. >

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates

Abstract: With finer line widths and faster switching speeds, the resistance of on-chip metal interconnect is having a dominant impact on the timing behavior of logic gates. Specifically, the gates are switching faster and the interconnect delays are getting longer due to scaling. This results in a trend in which the RC interconnect delay is beginning to comprise a larger portion of the overall logic stage delay. This shift in relative delay dominance from the gate to the RC interconnect is increased by resistance shielding. That is, as the gate "resistance" gets smaller and the metal resistance gets larger, the gate no longer "sees" the total net capacitance and the gate delay may be significantly less than expected. This trend complicates the timing analysis of digital circuits, which relies upon simple, empirical gate delay equations for efficiency. In this paper, we develop an analytical expression for the "effective load capacitance" of a pc interconnect. In addition, when there is significant shielding, the response waveforms at the gate output may have a large exponential tail. We show that this waveform tail can strongly influence the delay of the RC interconnect. Therefore, we propose an extension of the effective capacitance equation that captures the complete waveform response accurately, with a two-piece gate-output-waveform approximation. >

Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

Abstract: The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-/spl mu/m CMOS process with V/sub T/=/spl plusmn/0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV/sub ptp/ and a powerdrain of only 110 /spl mu/W. >

Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures

Abstract: Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation. >

CMOS active pixel image sensor

Abstract: A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 /spl mu/m double-poly, double-metal foundry CMOS process and is realized as a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications. >

Analysis of timing jitter in CMOS ring oscillators

Abstract: in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis shows that timing jitter is inversely proportional to the square root of the total capacitance at the output of each inverter, and inversely proportional to the gate-source bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with fixed output period. Phase noise and timing jitter performance are predicted to improve at a rate of 10 dB per decade increase in power consumption. >

A low-voltage CMOS DC-DC converter for a portable battery-operated system

Abstract: Motivated by emerging battery-operated applications that demand compact, lightweight, and highly efficient DC-DC power converters, a buck circuit is presented in which all active devices are integrated on a single chip using a standard 1.2 /spl mu/ CMOS process. The circuit delivers 750 mW at 1.5 V from a 6 V battery. To effectively eliminate switching loss at high operating frequencies, the power transistors achieve nearly ideal zero-voltage switching (ZVS) through an adjustable dead-time control scheme. The silicon area and power consumption of the gate-drive buffers are reduced with a tapering factor that minimizes short-circuit current and dynamic dissipation for a given technology and application. Measured results on a prototype IC indicate that on-chip losses at full load can be kept below 8% at 1 MHz. >

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

Abstract: This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2/spl pi/ radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface. >

Silicon:germanium heterojunction bipolar transistors: from experiment to technology

Abstract: Recent advances in thin film growth techniques, notably the maturation of low temperature silicon epitaxy, have enabled the routine fabrication of highly controlled dopant and silicon:germanium alloy profiles. These capabilities, combined with refinements in heterojunction bipolar transistor designs, have led to the first integrated circuits in the silicon:germanium materials system. Utilizing a commercial (Leybold-AG) UHVCVD tool for SiGe epitaxy on a standard 8" CMOS line, medium scale integration has been achieved, with the first IC components being SiGe HBT based 1 Ghz, 12 bit, digital to analog converters.

Adaptive photoreceptor with wide dynamic range

Abstract: We describe a photoreceptor circuit that can be used in massively parallel analog VLSI silicon chips, in conjunction with other local circuits, to perform initial analog visual information processing. The receptor provides a continuous-time output that has low gain for static signals (including circuit mismatches), and high gain for transient signals that are centered around the adaptation point. The response is logarithmic, which makes the response to a fixed image contrast invariant to absolute light intensity. The 5-transistor receptor can be fabricated in an area of about 70 /spl mu/m by 70 /spl mu/m in a 2-/spl mu/m single-poly CMOS technology. It has a dynamic range of 1-2 decades at a single adaptation level, and a total dynamic range of more than 6 decades. Several technical improvements in the circuit yield an additional 1-2 decades dynamic range over previous designs without sacrificing signal quality. The lower limit of the dynamic range, defined arbitrarily as the illuminance at which the bandwidth of the receptor is 60 Hz, is at approximately 1 lux, which is the border between rod and cone vision and also the limit of current consumer video cameras. The receptor uses an adaptive element that is resistant to excess minority carrier diffusion. The continuous and logarithmic transduction process makes the bandwidth scale with intensity. As a result, the total AC RMS receptor noise is constant, independent of intensity. The spectral density of the noise is within a factor of two of pure photon shot noise and varies inversely with intensity. The connection between shot and thermal noise in a system governed by Boltzmann statistics is beautifully illustrated. >

Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits

Abstract: As the number of transistors integrated on a circuit continues to increase, roughly doubling every 18 months, the impact of transistor variations on circuit performance becomes more significant. Even in the absence of systematic variations (implant nonuniformities, Leff and Weff variations), there exists a fundamental variability in the threshold voltage V/sub T/ due to the finite number of dopant atoms in the extremely small MOSFET channel area. This work presents for the first time the impact of these fundamental V/sub T/ variations on SRAM cell stability and CMOS logic performance. We also analyze the impact of device scaling on these V/sub T/ variations and propose guidelines for future SRAM cell design. >

VIKING, a CMOS low noise monolithic 128 channel frontend for Si-strip detector readout

Abstract: A low noise Si-strip detector readout chip has been designed and built in 1.5 μm CMOS technology. The chip is optimized w.r.t. noise. Measurements with this chip connected to several silicon strip detectors are presented. A noise performance of ENC = 135 e− + 12 e−/pF and signal to noise ratios between 40–80, depending on the detector, for minimum ionizing particles traversing 280 300 μ m silicon has been achieved.

A review of adiabatic computing

Abstract: We explain (a) why people want a low-energy computer; (b) under what conditions there is-or is not-an irreducible energy per computation for CMOS circuits; (c) partial versus full adiabatic computation, and their relationship to logically reversible computation; (d) various schemes for achieving adiabatic operation.

A CMOS area image sensor with pixel-level A/D conversion

Abstract: Charge-coupled devices (CCD) are at present the most widely used technology for implementing area image sensors. However, they suffer from low yields, consume too much power, and are plagued with SNR limitations due to the shifting and detection of analog charge packets, and the fact that data is communicated off chip in analog form. This paper describes an area image sensor that can potentially circumvent the limitations of CCDs and their alternatives. It uses a standard CMOS process and can therefore be manufactured with high yield. Digital circuitry for control and signal processing can be integrated with the sensor. Moreover, CMOS technology advances such as scaling and extra layers of metal can be used to improve pixel density and sensor performance. The analog image data is immediately converted to digital at each pixel using a one-bit sigma-delta modulator. The use of sigma-delta modulation allows the data-conversion circuitry to be simple and insensitive to process variations. A global shutter provides variable light input attenuation to achieve wide dynamic range. Data is communicated off chip in a digital form, eliminating the SNR degradation of analog data communication. To demonstrate the viability of the approach, an area image sensor chip is fabricated in a 1.2 /spl mu/m CMOS technology. The device consists of an array of 64x64 pixel blocks, a clock driver, a 6:64 row address decoder, 64 latched sense amplifiers, and 16 4:1 column multiplexers. The chip also contains data compression circuitry. >

An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis

Abstract: A novel way of implementing the leading zero detector (LZD) circuit is presented The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology The CMOS version was designed using both: logic synthesis and an algorithmic approach The algorithmic implementation is compared with the results obtained using modern logic synthesis tools in the same 06 /spl mu/m CMOS technology The implementation based on an algorithmic approach showed an advantage compared to the results produced by the logic synthesis ECL implementation of the 64 bit LZD circuit was simulated to perform in under 200 ps for nominal speed >

On latching probability of particle induced transients in combinational networks

Abstract: The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper An experimental method is presented in which the proportion of bit flips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally, estimated to be between 0.7/spl middot/10/sup -3/ and 2/spl middot/10/sup -3/ for a custom designed CMOS circuit. Very few multiple bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate. >

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Abstract: The two-dimensional discrete cosine transform (2D DCT) has been widely recognized as a key processing unit for image data compression/decompression. In this paper, the implementation of a 200 MHz 13.3 mm/sup 2/ 8/spl times/8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 /spl mu/m base-rule CMOS technology and 0.5 /spl mu/m MOSFET's, performs the DCT processing with 1 sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-F/F) circuit technique in combination with nMOS differential logic. The SA-F/F, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dual-rail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation. >

Current-mode CMOS multiple-valued logic circuits

Abstract: Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >

Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation

Abstract: A circuit technique to reduce threshold voltage fluctuation by a use of self-substrate-bias is introduced. The substrate bias is controlled so that leakage current of a representative MOSFET is adjusted constant with a feedback loop. The threshold voltage can be controlled within /spl plusmn/0.05 V and the speed gains under 1.5 V and 1V V/sub DD/ are estimated to be a factor of 1.3 and 3, respectively. A test chip is fabricated and effectiveness of the scheme is investigated. >

A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC

Abstract: This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-/spl mu/m CMOS process. The ADC operates at 600 ks/s using 45 mW of power at /spl plusmn/2.5 V supplies. The active die area excluding the external logic circuit is 1 mm/sup 2/. Maximum DNL of /spl plusmn/0.6 LSB and INL of /spl plusmn/1 LSB at a 12-b resolution have been achieved. >

A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS

Abstract: A CMOS test chip that includes a 1k-transistor self-testing encoder/decoder is verifiably error-free at supply voltages down to 20O mV, achieving 1/625 the power-delay product of standard 5 V CMOS. The maximum error-free operating frequency of this circuit as a function of supply and threshold voltage is reported here and voltage scaling of performance is compared with ring-oscillator data reported earlier. The circuit works even when bodies of transistors are forward-biased relative to sources to induce /spl sim/100mV depletion-mode thresholds. >

Noise in digital dynamic CMOS circuits

Abstract: Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits. >

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Abstract: For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

A single poly EEPROM cell structure for use in standard CMOS processes

Abstract: A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a "floating gate". The inversion layer as "control node (gate)". Test chips which were fabricated in a 0.8 /spl mu/m/150 /spl Aring/ standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits. >

Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay

Abstract: An improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered. These effects modify the ideal linear relationship between the inverter propagation delay and the input ramp rise/fall time by adding a term proportional to the charge supplied by the short-circuiting transistor. This term is shown to contain first- and second-order contributions of the input ramp rise/fall time where the second-order contribution effectively models the propagation delay roll-off for slow input ramps. Both the first and the second-order effects are found to be affected by the P-to-N-channel gain ratio. The model shows excellent agreement with SPICE level 3 simulations; even when the short-circuiting transistor has a driving capability twice that of the charging/discharging transistor the error in the propagation delay is only about 2% for a slow input ramp (input-to-output slope-ratio at V/sub DD//2 equal to 1:2). >

Design techniques for low-voltage high-speed digital bipolar circuits

Abstract: This paper describes design techniques for multigigahertz digital bipolar circuits with supply voltages as low as 1.5 V. Examples include a 2/1 multiplexer operating at 1 Gb/s with 1.2 mW power dissipation, a D-latch achieving a maximum speed of 2.2 GHz while dissipating 1.4 mW, two exclusive-OR gates with a delay less than 200 ps and power dissipation of 1.3 mW, and a buffer/level shifter having a delay of 165 ps while dissipating 1.4 mW. The prototypes have been fabricated in a 1.5-/spl mu/m 12-GHz bipolar technology. Simulations on benchmarks such as frequency dividers and line drivers indicate that, for a 1.5-V supply, the proposed circuits achieve higher speed than their CMOS counterparts designed in a 0.5-/spl mu/m CMOS process with zero threshold voltage. >

A Gate-Delay Model for High-Speed CMOS Circuits

Abstract: As signal speeds increase and gate delays decrease for high-performance digital integrated circuits, the gate delay modeling problem becomes increasingly more difficult. With scaling, increasing interconnect resistances and decreasing gate-output impedances make it more difficult to empirically characterize gate-delay models. Moreover, the single-input-switching assumption for the empirical models is incompatible with the inevitable simultaneous switching for today.s high-speed logic paths. In this paper a new empirical gate delay model is proposed. Instead of building the empirical equations in terms of capacitance loading and input-signal transition time, the models are generated in terms of parameters which combine the benefits of empirically derived k-factor models and switch-resistor models to efficiently: 1) handle capacitance shielding due to metal interconnect resistance, 2) model the RC interconnect delay, and 3)provide tighter bounds for simultaneous switching.

Driving a capacitive load without dissipating fCV/sup 2/

Abstract: Output pad drivers often contribute a large part of the total power dissipation of a chip, due to the large capacitive load they drive Here, we describe a driver capable of significant reduction of this dissipation, for given values of voltage swing, load capacitance, and switching frequency, without performance loss We accomplish this by stepwise charging, an inductor-free form of adiabatic charging

Inverter models of CMOS gates for supply current and delay evaluation

Abstract: The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well. >

A wide-dynamic-range, low-power photosensor array

Abstract: A 32/spl times/32 array of photosensors with pulse frequency outputs uses standard 2 /spl mu/m CMOS technology. The photosensors use pulse-frequency encoding to achieve a linear dynamic range of 10/sup 6/ in optical energy. Power dissipation of the photosensor is proportional to the frequency of the pulse outputs, and under typical illumination and bias conditions, the entire 32/spl times/32 array dissipates >