Showing papers on "Depletion region published in 1998"

Effect of temperature on Ga2O3(Gd2O3)/GaN metal–oxide–semiconductor field-effect transistors

Abstract: Ga2O3(Gd2O3) was deposited on GaN for use as a gate dielectric in order to fabricate a depletion metal–oxide–semiconductor field-effect transistor (MOSFET). Analysis of the effect of temperature on the device shows that gate leakage is significantly reduced at elevated temperature relative to a conventional metal–semiconductor field-effect transistor fabricated on the same GaN layer. MOSFET device operation in fact improved upon heating to 400 °C. Modeling of the effect of temperature on contact resistance suggests that the improvement is due to a reduction in the parasitic resistances present in the device.

2.6 kV 4H-SiC lateral DMOSFETs

Abstract: A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET.

MISFET semiconductor device having relative impurity concentration levels between layers

Abstract: A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n + -type semiconductor layer is formed in the prospective source and drain regions of the first semiconductor layer via the gate electrode, and a third n − -type semiconductor layer is formed on the second semiconductor layer. Each of source and drain regions is formed from the second and third semiconductor layers. The upper edge of the source/drain regions is formed above the boundary between the first semiconductor layer and the gate insulating film. In an ON state, part of a depletion layer in the drain region is formed in the third semiconductor layer, and part of a depletion layer in the source region is formed in the second semiconductor layer.

Silicon carbide field effect transistor with increased avalanche withstand capability

Abstract: A vertical SiC trench MOSFET power switching FET includes a gate electrode in the trench. The MOSFET adds a buried region of a first conductivity type, more heavily doped than a base layer of the first conductivity type, to the base layer except adjacent to the trench. The buried region is preferably disposed in the base layer, or between a drift layer of a second conductivity type and the base layer. The region of the first conductivity type is optionally disposed below the bottom of the trench to encourage expansion of the depletion layer of the MOSFET. A depletion-type vertical SiC MESFET of the invention includes a buried region of the first conductivity type in a base layer of a second conductivity type. A Schottky electrode on a portion of the base layer above the buried region ensures adequate expansion of a depletion layer.

Origin of conductivity and low-frequency noise in reverse-biased GaN p-n junction

Abstract: We study the origins of conductivity and low-frequency noise in GaN p-n junctions under reverse bias. Carrier hopping through defect states in the space charge region is identified as the main mechanism responsible for low bias conductivity. Threading dislocations appear the most likely source of such defect states. At higher bias hopping is supplemented with Poole–Frenkel emission. A relatively high level of 1/f-like noise is observed in the diode current. The bias and temperature dependencies of the noise current are investigated.

Influence of temperature and interface charge on the grain-boundary conductivity in acceptor-doped SrTiO3 ceramics

Abstract: The temperature dependence of both the grain-boundary potential barrier height and the conductivity across the grain-boundary space-charge depletion layer in acceptor-doped SrTiO3 ceramics has been investigated by a numerical simulation technique. The underlying model is that of a back-to-back double Schottky barrier at the grain boundary. The influence of the amount of positively charged donorlike grain-boundary interface states on the charge transport behavior of the grain-boundary region is also discussed. An interpretation in terms of a defect chemistry model of the bulk and the space-charge depletion layer, which on both sides surrounds the grain-boundary core is presented. The temperature behavior of the potential barrier at the grain boundary can be divided into three different regimes: a linear regime, and subsequently, saturation and decreasing regimes. The theoretical explanation for this behavior is given. Two different spatial conductivity profiles at the grain boundaries have to be considered...

Low-frequency noise and performance of GaN p-n junction photodetectors

Abstract: We report on low-frequency noise characteristics of visible-blind GaN p-n junction photodetectors. Carrier hopping through defect states in the space charge region, believed to be associated with dislocations, is identified as the main mechanism responsible for the dark conductivity of the photodiodes. Under reverse bias, the dark current noise has the 1/f character and obeys the Hooge relation with α≈3. Under forward bias, we observe generation-recombination noise related to a trap level with the activation energy of 0.49 eV. Under illumination, detectivity is found to be shot noise limited. The noise equivalent power of a 200×200 μm2 photodetector is estimated at 6.6×10−15 W/Hz1/2 at a bias of −3 V.

Amorphous silicon carbide/crystalline silicon heterojunction solar cells :a comprehensive study of the photocarrier collection

Abstract: We have studied the current–voltage (I–V) characteristics of p+ a-SiC:H/n c-Si heterojunction solar cells at different conditions. Under standard test conditions (300 K, 100 mW/cm2, AM1.5) these cells show normal I–V characteristics with a high fill factor (FF = 0.73) and a relatively high efficiency for their simple structure (η≈13%). However, below room temperature and at illumination levels above 10 mW/cm2 they exhibit an S-shaped I–V curve and a low fill factor. Simulation studies revealed that this effect is caused by the valence band discontinuity at the amorphous/crystalline interface which hinders at low temperatures the collection of photogenerated holes at the front contact. At low temperatures a high hole accumulation at the interface combined with extra trapping of holes inside the p+ a-SiC:H layer causes a shift of the depletion region, from the c-Si into the p+ a-SiC:H. This leads to an enhanced recombination inside the c-Si depletion region causing a significant current loss (S-shape). Tunnelling through the valence band spike can reduce these effects. For lower doped p a-SiC:H layers (Eact>0.4 eV) this S-shape can even occur at room temperature.

Aging Mechanisms of InGaN/AlGaN/GaN Light-Emitting Diodes Operating at High Currents

Abstract: Changes of luminescence spectra and electrical properties of light-emitting diodes (LED’s) based on InGaN/AlGaN/GaN heterostructures were investigated over a long period of operation. Blue and green LED’s with InGaN single quantum wells were studied at currents up to 80 mA for 102−2.103 hours. An increase of luminescence intensity at operating currents of 15 mA was detected at the 1st stage of aging (100–800 hours) and a slow fall was detected in the 2nd stage. Greater changes of spectra were observed at low currents (< 0.15 mA). A study of charged acceptor distribution in the space charge region has shown that at the 1st stage their concentration grows, and in the 2nd stage, it falls. The models for the two stages are proposed: 1) activation of Mg due to destruction of residual Mg-H complexes; 2) formation of donor vacancies N. A model of defect formation by hot electrons injected into the quantum well is discussed.

Direct evidence of impact excitation and spatial profiling of excited Er in light emitting Si diodes

Abstract: We provide direct evidence that Er ions incorporated in the depletion layer of a p+–n+ Si junction are efficiently pumped through an impact excitation process with hot carriers. The carriers were accelerated by the electric field present in the depletion layer after being produced by either Zener breakdown of the junction at ∼5 V or by irradiating the diode with an argon laser. Measurements of the electroluminescence yield at 1.54 μm as a function of the reverse bias voltage (and for a constant current through the device) reveal that excitation of Er only occurs at voltages above 1 V, demonstrating that impact is the pumping mechanism. Moreover, we have found that Er ions are only excited within ∼15 nm from the edges of the depletion layer leaving a dark, ∼50 nm thick, region in the central part of the depletion region. Monte Carlo calculations confirmed that only close to the depletion layer edges the energy gained by the carriers in the electric field is high enough to impact excite Er.

Direct measurement of gate depletion in high breakdown (405 V) AlGaN/GaN heterostructure field effect transistors

Abstract: A new measurement technique that directly reveals the extent of the gate depletion region in FETs by using floating Schottky gates as potential probes is presented. Measurements on GaN heterojunction field heterojunction field effect transistors (HFETs) show that large extension of the depletion width is responsible for the high dc breakdown voltages in these HFETs.

Temperature Dependence of the Ideality Factor of Ba1-xKxBiO3/Nb-doped SrTiO3 All-Oxide-Type Schottky Junctions.

Abstract: Current-voltage measurements were performed on Ba1-xKxBiO3/Nb-doped SrTiO3 (BKBO/STO:Nb) all-oxide-type Schottky junctions in the temperature range of 30 to 300 K. The relative permittivity er(E, T) of undoped SrTiO3(110) was measured as a function of both temperature and electric field. An anomalous increase in ideality factor n(T) and decrease in zero-bias barrier height Φb0(T) with decreasing temperature were observed and were analyzed using the interfacial layer model with a thin insulating interfacial layer present between metal contact (BKBO) and semiconductor interface (STO:Nb). The increase in n(T) at low temperature can be explained by taking into account the temperature dependence of the permittivity of the depletion layer (STO:Nb). The effect of the electric field dependence of the permittivity of STO:Nb on n(T) is also discussed using an approximate electric field dependence, er(T, E)=b/(a+E2)1/2, where a and b are constants.

Photodiode DC and microwave nonlinearity at high currents due to carrier recombination nonlinearities

Abstract: We present photodetector compression measurements to demonstrate the consequences of absorption in undepleted regions close to the depletion region of p-i-n photodiodes. This absorption can modify the frequency response of photodetectors operating above a few milliamperes. The frequency response shows power dependence and additional ripple and rolloff.

An analytical model for the organic field-effect transistor in the depletion mode. Application to sexithiophene films and single crystals

Abstract: Organic field-effect transistors (OFETs) usually operate in the accumulation mode, where the biasing of the gate induces the charging of the insulator-semiconductor interface; the bias is negative in the most common case of p-type semiconductors. We show here that the application of a positive gate bias leads to the formation of a depletion layer, and a subsequent decrease of the drain current. We develop an analytical model for this depletion mode of the OFET. It is shown that measurements in the depletion mode give access to parameters such as the doping level and the density of trap levels. The model is applied to data obtained on sexithiophene (6T) film and single crystal OFETs. A substantial amount of traps is found in unsubstituted 6T, whereas the dihexyl substituted 6T is practically trap free. 6T single crystals are characterized by a very low doping level, which can be related to their very high purity. The possible use of the depletion mode to increase the on-off current ratio of OFETs is discussed.

An investigation of the spatial location of proton-induced traps in SiGe HBTs

Abstract: The effects of 46 MeV proton irradiation induced trap generation and its impact on the electrical characteristics of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) from an advanced ultrahigh vacuum/chemical vapor deposition (UHV/CVD) SiGe BiCMOS technology are examined and discussed for the first time. At proton fluences as high as 10/sup 14/ p/cm/sup 2/ the peak current gain of the devices degraded by less than 8% compared to the pre-irradiated samples. The maximum oscillation frequency and cutoff frequency of the SiGe HBTs showed only minor degradation after 10/sup 14/ p/cm/sup 2/. Calibration of 2-D device simulation (MEDICI) to measured data in both forward and inverse modes of operation was used to infer the spatial location of the proton-induced traps. Traps in the collector-base space charge region appear as generation/recombination (G/R) centers in the inverse emitter-base region and are the result of displacement damage. Traps at the emitter-base spacer oxide interface appear as G/R centers in the forward emitter-base space charge region and are the result of ionization damage. Taken together, these results suggest that UHV/CVD SiGe HBT technology is robust to proton fluences at least as high as 10/sup 13/ p/cm/sup 2/ without radiation hardening.

Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.

Performance of a CMOS compatible lateral bipolar photodetector on SOI substrate

Abstract: The performance of a photodetector fabricated using a standard CMOS process on SOI substrate has been studied. The photodetector is basically a floating gate SOI NMOSFET operating in the lateral bipolar mode. The depletion region induced by the floating gate separates the optically generated electron-hole pairs in the direction perpendicular to the current. This results in an extra current amplification beyond that of a normal lateral bipolar transistor. A high responsivity of 289 A/W has been measured with an operating voltage as low as 0.1 V. The impacts of technology scaling on the performance of the photodetector are also studied.

Solid-state image pickup device

Abstract: PROBLEM TO BE SOLVED: To realize a smaller device by adjusting the voltage applied to a semiconductor substrate by means of a voltage adjusting section, controlling the length of a depletion layer in a photoelectric transducing section, and electrically changing spectral sensitivity, without selecting the wavelength band of received light by a variable filter. SOLUTION: In a solid-state image-pickup device 1, electric charges accumulated in a photoelectric transducing section 11 are transferred by electric charge transferring sections 12. The photoelectric transducing section 11 is composed of an n+ region on the substrate surface side of a p-well region 10a in a substrate 10 made of n-type semiconductor, and the voltage applied to the substrate 10 is adjusted by a voltage- adjusting section 13. An overflow drain 14 is disposed on the opposite side of the photoelectric transducing section 11 to the electric charge transferring sections 12 corresponding to the photoelectric transducing section 11. A predetermined bias voltage is applied so as to adjust the saturated amount of signal of the photoelectric transducing section 11. A predetermined voltage is applied to the substrate 10 from the voltage-adjusting section 13, in response to a switching signal S, the height of an overflow barrier in the photoelectric transducing section is adjusted according to the voltage, and the length of a depletion layer is adjusted so as to control spectral sensitivity.

Very thin film capacitor for dynamic random access memory (DRAM)

Abstract: A capacitor and a dynamic random access memory (DRAM) incorporating such a capacitor, includes a first layer of conducting, doped perovskite material, a second layer of another conducting, doped perovskite of opposite polarity in contact with the first layer, and a depletion layer formed at an interface between the first and second layers of conducting perovskite materials, the depletion layer being an insulating layer of the capacitor. Another capacitor and DRAM incorporating such a capacitor, includes a first electrode, a second electrode opposing the first electrode, and a thin-film of high dielectric constant perovskite material sandwiched between the first and second electrodes. At least one of the first and second electrodes is formed from substantially the same perovskite material, as the thin-film, in conducting, doped form.

Electronic device, in particular for switching electric currents, for high reverse voltages and with low on-state losses

Abstract: A p-n junction is connected between two terminals. The p-n junction is formed between two semiconductor regions of a semiconductor with a breakdown field strength of at least 106 V/cm. A channel region, which adjoins the p-n junction is connected in series with a silicon component between the two terminals. The channel region is provided in a first of the two semiconductor regions. A depletion zone of the p-n junction carries the reverse voltage in the off state of the silicon component. The silicon component is preferably a

The dissociation energy and the charge state of a copper-pair center in silicon

Abstract: Thermal dissociation of Cu pairs was studied in p-type silicon. The dissociation energy of the Cu pair was found to be 1.02±0.07 eV, twice as high as the binding energy of a Coulombically bound donor-acceptor pair placed on nearest neighbor 〈111〉 sites. This implies that the pair is either covalently bonded, or it consists of an ionically bonded doubly negatively charged acceptor and a singly charged donor. To distinguish between these two models, the dependence of the hole emission rate on the electric field in the depletion region was studied. The absence of the Pool-Frenkel emission enhancement ruled out the acceptor nature of the center and the purely ionic type of bonding. On the other hand, the polarization potential describing emission from a neutral impurity gave a satisfactory fit to the experimental data. It is concluded that the Cu pair is a donor with either covalent or mixed type of bonding.

Optically-controlled ion-implanted GaAs MESFET characteristic with opaque gate

Abstract: An analytical modelling has been carried out for an ion-implanted GaAs MESFET having a Schottky gate opaque to incident radiation. The radiation is absorbed in the device through the spacings of source, gate, and drain unlike the other model where gate is transparent/semitransparent. Continuity equations have been solved for the excess carriers generated in the neutral active region, the extended gate depletion region and the depletion region of active (n) and substrate (p) junction. The photovoltage across the channel and the p-layer junction and that across the Schottky junction due to generation in the arc region of the gate depletion layer are the two important controlling parameters. The I-V characteristics and the transconductance of the device have been evaluated and discussed.

Improved neutron radiation hardness for Si detectors: application of low resistivity starting material and/or manipulation of N/sub eff/ by selective filling of radiation-induced traps at low temperatures

Abstract: Radiation-induced electrical changes in both the space charge region (SCR) of Si detectors and bulk material (BM) have been studied for samples of diodes and resistors made on Si materials with different initial resistivities. The space charge sign inversion fluence (/spl Phi//sub inv/) has been found to increase linearly with the initial doping concentration (the reciprocal of the resistivity), which gives improved radiation hardness to Si detectors fabricated from low resistivity material. The resistivity of the BM, on the other hand, has been observed to increase with the neutron fluence and approach a saturation value in the order of hundreds k/spl Omega/cm at high fluences, independent of the initial resistivity and material type. However, the fluence (/spl Phi//sub s/), at which the resistivity saturation starts, increases with the initial doping concentrations and the value of /spl Phi//sub s/ is in the same order of that of /spl Phi//sub inv/ for all resistivity samples. Improved radiation hardness can also be achieved by the manipulation of the space charge concentration (N/sub eff/) in SCR, by selective filling and/or freezing at cryogenic temperatures the charge state of radiation-induced traps, to values that will give a much smaller full depletion voltage. Models have been proposed to explain the experimental data.

How big are charge clouds inside the charge-coupled device produced by x-ray photons?

Abstract: We report here the charge cloud shape produced by an X-ray photon inside the charge-coupled device (CCD) as well as a method to measure it. The measurement is carried out by using a multi-pitch mesh which enables us to specify the interaction position of X-rays with subpixel resolution not only for single events but also for split events. Split events are generated when the X-ray interaction position is close to the pixel boundary. The width of this area depends on the apparent charge size. Finally, we measured the signal output from the pixel according to the interaction position of X-rays. By differentiating this function, we obtain, in detail, the charge cloud shape which can be well represented by an asymmetric Gaussian function. The charge cloud size for Al-K X-rays is 0.7×1.4 µm2 while that for Mo-L X-rays is 0.8×1.4 µm2. The size of the photoelectron in Si produced by these X-rays is about 0.04 µm. Taking into account the mean absorption length for these X-rays in Si, diffusion process in the depletion region cannot explain the charge cloud size. The asymmetry of the charge cloud probably arises from the asymmetry of the electric field in the CCD.

Transient ion-drift-induced capacitance signals in semiconductors

Abstract: A theoretical model is developed that describes capacitance signals induced by drift of mobile ions in the space charge region of a Schottky diode. Pairing between the diffusing ion and the doping impurities is taken into account. The coupled partial differential equations are resolved numerically and the influence of key parameters on the signal shape is analyzed. Special emphasis is put on those features that enable transient ion-drift- (TID-) induced signals to be distinguished from capacitance transients caused by deep-level carrier emission processes. Relaxation kinetics and reverse bias dependence of the signal shape represent two reliable tools to verify the ion-drift nature of the signals. Methods for extracting quantitative information on both diffusion and pairing properties of the mobile ions are described. The question of whether pairing or diffusion is limiting the process is addressed. The influence of the doping level on the signal time constant is used to evaluate whether or not the diffusion is trap limited. A semiempirical model is described that permits the estimation of diffusion and pairing coefficients without resolving numerically the differential equations. Experiments are performed on interstitial copper in {ital p}-type silicon to test the predictions of the theoretical model. An overall agreement ismore » found between theory and experiments. {copyright} {ital 1998} {ital The American Physical Society}« less

Method for producing bridged, doped zones

Abstract: Bridged, doped zones are formed in a semiconductor. A silicon nitride layer is deposited and structured on a semi-conductor region with a predetermined dopant concentration. The structure is subjected to thermal oxidation, with the result that at least one oxide region and at least two oxide-free regions, which are separated from one another by the oxide region, are produced on the surface of the semiconductor region. A dopant is introduced into the oxide-free regions and driven into the semiconductor region. A coherent zone is thus produced in the semiconductor region with a dopant concentration at least ten times the dopant concentration of the semiconductor region. This produces a coherent zone having a high dopant concentration which is bridged by the oxide region which separates the oxide-free regions on the surface of the semiconductor region. Conductive layers, such as a polysilicon layer or a metal layer, for example, can be formed on the oxide region (oxide bridge), with the assurance the conductive layer is completely insulated from the doped zone.

Current-limiting semiconductor configuration

Abstract: A semiconductor configuration includes a first semiconductor region which has a predetermined conductivity type and a first surface. There is a contact region disposed on the first surface of the first semiconductor region. There is a second semiconductor region disposed within the first semiconductor region underneath the contact region which has a conductivity type opposite the predetermined conductivity type of the first semiconductor region. A first p-n junction having a first depletion zone is formed between the first semiconductor region and the second semiconductor region. The second semiconductor region extends further than the contact region in all directions parallel to the first surface of the first semiconductor region to form at least one lateral channel region with a bottom in the first semiconductor region. The at least one lateral channel region is bounded toward its bottom by the first depletion zone of the first p-n junction. In an on state of the semiconductor configuration, the at least one lateral channel region conducts an electric current from the contact region or to the contact region.