Showing papers on "Dopant Activation published in 2003"
TL;DR: In this paper, it was shown that poly-SiGe layers are an attractive alternative to low-pressure CVD (LPCVD) polySi or polySiGe because of their high growth rate (100-200 nm/min) and low deposition temperature (520/spl deg/C-590/spl dc/C) for use in microaccelerometers, microgyroscopes or for thin-film encapsulation.
Abstract: Thick poly-SiGe layers, deposited by plasma-enhanced chemical vapor deposition (PECVD), are very promising structural layers for use in microaccelerometers, microgyroscopes or for thin-film encapsulation, especially for applications where the thermal budget is limited. In this work it is shown for the first time that these layers are an attractive alternative to low-pressure CVD (LPCVD) poly-Si or poly-SiGe because of their high growth rate (100-200 nm/min) and low deposition temperature (520/spl deg/C-590/spl deg/C). The combination of both of these features is impossible to achieve with either LPCVD SiGe (2-30 nm/min growth rate) or LPCVD poly-Si (annealing temperature higher than 900/spl deg/C to achieve structural layer having low tensile stress). Additional advantages are that no nucleation layer is needed (deposition directly on SiO/sub 2/ is possible) and that the as-deposited layers are polycrystalline. No stress or dopant activation anneal of the structural layer is needed since in situ phosphorus doping gives an as-deposited tensile stress down to 20 MPa, and a resistivity of 10 m/spl Omega/-cm to 30 m/spl Omega/-cm. With in situ boron doping, resistivities down to 0.6 m/spl Omega/-cm are possible. The use of these films as an encapsulation layer above an accelerometer is shown.
41 citations
TL;DR: In this article, a special attention has been paid to in situ and ex situ optical diagnostics in order to follow the laser induced phenomena, which highly depends on the implanted ion and dose, and the dopant activation are real time monitored by transient reflectivity (TR) at 675nm.
26 citations
TL;DR: In this paper, 6H and 4H-SiC were Al implanted with various doses to form p-type layers after a postimplantation annealing performed at 1700°C/30 min.
Abstract: Epilayers of 6H and 4H–SiC were Al implanted with various doses to form p-type layers after a postimplantation annealing performed at 1700 °C/30 min. Rutherford backscattering spectrometry in the channeling mode analyses carried out before and after annealing show virgin nonimplanted equivalent spectra if the implanted layers are not amorphized. The amorphous layers are recrystallized after annealing with a residual damage level of the lattice relative to the quantity of the dopant implanted. Secondary ion mass spectrometry measurements performed on the implanted samples before and after annealing illustrate a good superposition of the profiles obtained before and after the annealing on nonamorphized samples. Dopant redistribution occurs after annealing, only on amorphized layers, with an intensity that increases with the implanted dose. Deduced from sheet resistance measurements, the dopant activation increases with the implanted dose. Activation of 80%–90% is obtained from capacitance–voltage measuremen...
25 citations
TL;DR: In this article, the authors find that increasing the heating rate permits clusters with dissociation energies lower than the maximum of 3.5-3.7 eV to survive to higher temperatures.
Abstract: Use of high ramp rates (>400°C/s) in rapid thermal annealing after ion implantation leads to experimentally observed improvements in junction depth and the reverse narrow-channel effect. However, a straightforward explanation for this effect has been lacking. Via modeling, we find that increasing the heating rate permits clusters with dissociation energies lower than the maximum of 3.5-3.7 eV to survive to higher temperatures. This improved survival delays the increase in Si interstitial concentrations near the top of an annealing spike, which decreases the profile spreading.
24 citations
TL;DR: In this paper, the results of an ab initio study of N and P dopants in SiC were reported, showing that while N substitutes most favorably at a C lattice site, P does so preferably at a Si site, except in n-doping and Si-rich 3C-SiC.
Abstract: We report the results of an ab initio study of N and P dopants in SiC. We find that while N substitutes most favorably at a C lattice site, P does so preferably at a Si site, except in n-doping and Si-rich 3C-SiC. Furthermore, we consider a series of dopant complexes that could form in high-dose implantation, in order to investigate the dopant activation behavior in this limit. We find that all N complexes considered lead to passivation through the formation of a deep level. For P, the most stable aggregate is still an active dopant, while passivation is only observed for complexes with a higher formation energy. We discuss how these results could help in the understanding of the observed experimental high-dose doping and codoping behavior of these species.
24 citations
TL;DR: In this paper, the n-channel metal oxide semiconductor field effect transistor (n-MOS) and p-channel MOS transistors with width/length of 0.3/0.1 μm were fabricated in a single grain of recrystallized silicon, at low temperatures.
Abstract: In this work, we report high performance, 0.1 μm complementary metal oxide semiconductor (CMOS) transistors fabricated in a single grain of recrystallized silicon, at low temperatures. Metal induced crystallization (MIC) of amorphous silicon (a-Si) thin film and dopant activation was achieved simultaneously using nickel with a peak processing temperature of 500°C. The n-channel metal oxide semiconductor field effect transistor (n-MOS) and p-channel-MOS (p-MOS) devices with width/length of 0.3/0.1 μm show on-currents of 150 and 100 μA/μm, respectively, at a V DD of 2 V, without any optimization. These transistors are some of the best devices fabricated using MIC with 500°C limitation of processing temperature. They show excellent on-currents, subthreshold slope, and on/off current ratio with a simple device structure. They constitute a promising step toward matching the performance of bulk-Si CMOS.
15 citations
TL;DR: Yeo et al. as mentioned in this paper performed both front and backside depth profiling using 0.5 keV O2+ with oxygen flooding and 2 keV Cs+ primary ions at oblique incidence in a Cameca IMS-6f SIMS instrument.
Abstract: High drive-in temperature during dopant activation of p+-poly metal-oxide-semiconductor field effect transistors causes boron penetration through the thin gate oxide, which degrades the device performance. Conventional secondary ion mass spectrometry (SIMS) depth profiling is unable to accurately analyze boron penetration under rapid thermal annealing conditions due to ion knock-on and mixing effects. With the development of backside SIMS depth profiling technique using SOI wafers [Yeo et al., Surf. Interface Anal. 33, 373 (2002); Runsheim et al., J. Vac. Sci. Technol. B 20, 448 (2002)], quantification of the amount of boron penetration becomes possible. In this article, boron penetration through decoupled plasma nitridation silicon dioxide was studied by performing both front and backside depth profiling using 0.5 keV O2+ with oxygen flooding and 2 keV Cs+ primary ions at oblique incidence in a Cameca IMS-6f SIMS instrument.
13 citations
01 Jan 2003
TL;DR: In this article, the conditions necessary for fabricating both reproducible I-V characteristics and junction depths were investigated. But the conditions for fabricated I-v characteristics were not discussed.
Abstract: Near-ideal n + p and p + n diodes have been fabricated with excellent uniformity by implanting 5 keV As + and BF 2 + , respectively, and applying high-power excimer laser annealing for dopant activation. Four types of electrical measurements have been used to understand the conditions necessary for fabricating both reproducible I-V characteristics and junction depths: diode I-V characteristics, contact resistance measurements, CV-doping profiling of the p + n diode junction depth, and implanted polysilicon resistor measurement to monitor the laser beam uniformity.
11 citations
TL;DR: In this paper, scanning capacitance microscopy has been used to determine the concentration profiles of implanted 6H-SiC samples in a conventional furnace with a low ramp rate and with a high ramp rate (200 °C/s).
Abstract: Scanning Capacitance Microscopy has been used to determine the carr ier concentration profiles of N implanted 6H-SiC samples. The implantation dose and tar get temperature was chosen to avoid the formation of extended defects after annealing. Thermal t eatments were performed directly in a conventional furnace with a low ramp rate (0.05°C/s) and with a high ramp rate (200 °C/s). When performing high ramp rate thermal processes before the conv ntional furnace a higher activation occurs.
9 citations
TL;DR: In this paper, electron holography was used as a quantitative characterization tool for nanoscale charge distributions associated with ultra-shallow PN junctions in Si, which are needed for fabricating nano-scale MOSFETs, Si quantum dots and single electron transistors.
Abstract: This study extends electron holography as a quantitative characterization tool for nanoscale charge distributions associated with ultra shallow PN junctions in Si, which are needed for fabricating nanoscale MOSFETs, Si quantum dots and single electron transistors. The ultra shallow junctions were fabricated using rapid thermal diffusion from a heavily doped n-type surface source onto a heavily doped p-type substrate. Chemical characterization of the dopant profiles was performed using secondary ion mass spectrometry, which were analyzed to derive the metallurgical junction depth. 1-D characterization of the electrical junction depth associated with the electrically activated fraction of the incorporated dopants was performed using off-axis electron holography in a transmission electron microscope. 1-D potential profiles across the p–n junctions derived from electron holographic analysis were used to calculate the electric field and total charge distributions in the space charge region of the p–n junctions using numerical derivatives. Quantitative comparison between calculated electric field and total charge from the measured potential profiles and the simulated distributions using the secondary ion mass spectrometry profiles provide a reasonable estimate of the electrical activation of dopants in the ultra shallow junctions considered for this investigation.
7 citations
Patent•
TSMC1
TL;DR: In this paper, a new process integration method is described to form heavily doped p + source and drain regions in a CMOS device, after defining the p- and n-well regions on a semiconductor substrate, gate silicon dioxide is deposited and nitrided in a nitrogen-containing atmosphere.
Abstract: A new process integration method is described to form heavily doped p + source and drain regions in a CMOS device. After defining the p- and n-well regions on a semiconductor substrate, gate silicon dioxide is deposited and nitrided in a nitrogen-containing atmosphere. Poly-silicon is then deposited and the two NMOS and PMOS gates are formed. For the p + doping of the poly-silicon gate and S/D regions around the PMOS gate, B + ions are then implanted. Cap dielectric layer comprising silicon dioxide is then deposited, followed by dopant activation with high temperature rapid thermal annealing. The cap dielectric layer is then used as resist protective film; it is removed from those areas of the chip that would require formation of electrical contacts. Silicide electrical contacts are then formed in these areas.
Patent•
30 Oct 2003TL;DR: In this paper, a calcium doped polysilicon gate electrode for PMOS containing semiconductor devices is proposed to reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate.
Abstract: A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.
TL;DR: In this article, a 1-dimensional characterization of the electrical junction depth associated with the electrically activated fraction of the incorporated dopants was performed using off-axis electron holography in a transmission electron microscope.
Abstract: This investigation attempts quantitative characterization of ultra-shallow junctions (USJs) in Si, useful for future generations of nanoscale MOSFETs as predicted by the Semiconductor Industry Association Roadmap. The USJs were fabricated using rapid thermal diffusion (RTD) from a heavily doped n-type surface source onto a heavily doped p-type substrate. The dopant profiles were analyzed using secondary ion mass spectrometry (SIMS), and were further used to calculate the metallurgical junction depth (MJD). One-dimensional (1-D) characterization of the electrical junction depth (EJD) associated with the electrically activated fraction of the incorporated dopants was performed using off-axis electron holography in a transmission electron microscope. 1-D potential profiles were derived from the unwrapped phase of the reconstructed holograms. The EJD was derived from the measured potential distribution across the p-n junction, and quantitative comparison is made with MJD derived from the SIMS profiles. The comparison between calculated electric field and total-charge distributions from the measured potential profiles and the simulated distributions using the SIMS profiles provides a quantitative estimate of the electrical activation of dopants incorporated by the RTD process, within the accuracy limits of this technique, which is discussed herein.
TL;DR: In this paper, the electrical properties and microstructures of n-type doped poly films with Ge contents were investigated using hall measurement, four-point probe, transmission electron microscopy, and energy dispersive X-ray spectrometry to apply to gate electrode of complementary metal oxide semiconductor field effect transistor.
Abstract: We investigated the electrical properties and microstructures of n-type doped poly films with Ge contents using hall measurement, four-point probe, transmission electron microscopy, and energy dispersive X-ray spectrometry to apply to gate electrode of complementary metal oxide semiconductor field effect transistor. The sheet resistance of poly films implanted with arsenic decreased with the decrease of Ge content and the increase of activation temperature due to the increase of carrier mobility and activated carrier concentration. In addition, we found that the segregation of dopant increased at the grain edge and the activated carrier concentration decreased with the increase of Ge content due to higher diffusivity and lower solid solubility limit of As in poly films. © 2003 The Electrochemical Society. All rights reserved.
Patent•
02 Jul 2003
TL;DR: In this article, a fabrication method of semiconductor devices is provided to reduce a resistance and to improve a dopant activation ratio of P-type source and drain by controlling dose of fluorine(F).
Abstract: PURPOSE: A fabrication method of semiconductor devices is provided to reduce a resistance and to improve a dopant activation ratio of P-type source and drain by controlling dose of fluorine(F). CONSTITUTION: After forming an isolation layer(22) in a silicon substrate(21) using an STI(Shallow Trench Isolation), a gate oxide(24) and a gate electrode(25) are formed on the resultant structure. After forming spacers(27) at both sidewalls of the gate electrode, a photoresist pattern(28) is coated on the resultant structure so as to expose source and drain regions. The source and drain regions are transferred to pre-amorphous layer by implanting dopants of BF2 and then B dopants are implanted by using the photoresist pattern as a mask, thereby forming a p+ source/drain(29). At this time, the dose of the BF2 dopants is 1x1015 - 2x1015 ions/cm¬2, and the dose of the B dopants is 1x1015 - 2 x1015 ions/cm¬2.
01 Jan 2003
TL;DR: In this article, the effect of non-uniformity in sheet resistance measurements on the front side of a wafer was investigated with patterned test wafers annealed in lamp-based and conductive heating RTP systems.
Abstract: Emissivity variations on the front side of a wafer are due to the different materials present on patterned wafers. When using high ramp rates rapid thermal processing dopant activation at high temperature can cause temperature non-uniformity within a die. We show this effect with patterned test wafers annealed in lamp-based systems and in a conductive heating RTP system (ASM Levitor) [1]. We confirm our previous work obtained with sheet resistance measurements. SIMS profiles measured at different locations of a die show slight variation for a deep 5 keV boron implantation. Oxidation growth on the lamp based system results in a 10 % thickness variation between the centre and the edge of a die. Van der Pauw structures implanted either with n-type or p-type dopant shows fluctuations in the sheet resistance along a die in the lamp-based system. However, this effect is negligible on the tool using conductive heating.
TL;DR: In this paper, the effect of a nitride diffusion mask on lateral diffusion of phosphorous is discussed and compared to the lateral diffusion under an oxide diffusion mask, and the results obtained on 2D electrical characterization of ultra shallow junctions in Si using off axis electron holography to study two-dimensional effects on diffusion.
TL;DR: In this article, it is demonstrated that when the laser fluence is adjusted to a value that can melt the preamorphization implantation (PAI) layer but not the underlying silicon substrate, PAI layer depths control the junction depths.
Abstract: One of the major advantages of multiple-pulses Laser Thermal Annealing (LTA) with moderate energy fluence is that good dopant activation can be achieved without further increases in junction depth by successive pulses. It is demonstrated that when the laser fluence is adjusted to a value that can melt the preamorphization implantation (PAI) layer but not the underlying silicon substrate, PAI layer depths control the junction depths. Hence, it is desirable to operate LTA in this regime since this allows for a tighter process control as opposed to when the junction depth is controlled solely by the laser fluence. High Resolution Transmission Electron Microscopy (HR-TEM) micrographs show that the degree of damage repair depends on the amorphous layer thickness as well as the number of pulses. Our study allows for the evaluation of the maximum allowable PAI depth for a given number of pulses in order to fully remove the damage caused by the PAI.
TL;DR: In this paper, the authors have fabricated bottom gate TFTs with poly-Si and poly- Si1-xGex thin films deposited at 450°C by newly developed low-temperature LPCVD technique.
Abstract: In the fabrication of thin film transistors (TFTs), little attention has been paid to the polycrystalline silicon thin films prepared at low temperatures where the glass substrates are adopted so far. Since the film quality is not sufficient to achieve high mobility, e.g., over 50 cm2/Vs in spite of high benefit in their industrial fabrication. We have fabricated bottom gate TFTs with poly-Si and poly- Si1-xGex thin films deposited at 450°C by newly developed low-temperature LPCVD technique and characterized electrical characteristics of the TFTs: disilane and a small amount of either germanium tetrafluoride or fluorine were used as material gases and helium as carrier gas. Thermal annealing for dopant activation and atomic hydrogen treatment for defect passivation were carried out. We found that the defect elimination process is important for improving TFT performance significantly. Finally the mobility of p-channel and n-channel TFTs have attained 36.3-54.4 cm2/Vs and 57 cm2/Vs, respectively.
Patent•
21 May 2003
TL;DR: In this article, a semiconductor wafer is irradiated with laser energy sufficient to activate the dopant material without melting the wafer, and rapid thermal annealing is performed at relatively low temperature to repair crystalline damage.
Abstract: Methods are provided for thermal processing of a semiconductor wafer that contains a dopant material. The wafer is irradiated with laser energy sufficient to activate the dopant material without melting the wafer. In addition, rapid thermal annealing of the wafer is performed at relatively low temperature to repair crystalline damage. The dopant activation is achieved with no measurable diffusion. The low temperature rapid thermal anneal repairs crystalline damage, so that devices have good mobilities and low leakage currents.
Patent•
09 Aug 2003
TL;DR: In this article, a semiconductor wafer is irradiated with laser energy sufficient to activate the dopant material without melting the wafer, and rapid thermal annealing is performed at relatively low temperature to repair crystalline damage.
Abstract: Methods are provided for thermal processing of a semiconductor wafer that contains a dopant material. The wafer is irradiated with laser energy sufficient to activate the dopant material without melting the wafer. In addition, rapid thermal annealing of the wafer is performed at relatively low temperature to repair crystalline damage. The dopant activation is achieved with no measurable diffusion. The low temperature rapid thermal anneal repairs crystalline damage, so that devices have good mobilities and low leakage currents.
TL;DR: In this article, the effect of post-implant annealing on the optical and electrical properties of Si-implanted GaN films was investigated, and the results from several measurement techniques including room temperature photoluminescence (PL), micro-Raman scattering, high resolution X-ray diffraction (HRXRD) and Hall measurement were correlated to study the behavior of damage removal, dopant activation, crystalline quality and residual stress, etc.
Abstract: In this paper, we investigate the effect of post-implant annealing on the optical and electrical properties of Si-implanted GaN films. Results from several measurement techniques including room temperature photoluminescence (PL), micro-Raman scattering, high resolution X-ray diffraction (HRXRD) and Hall measurement are correlated to study the behavior of damage removal, dopant activation, crystalline quality and residual stress, etc. The Hall measurement demonstrates that reasonable activation percentage is achieved though there is only partial recovery of the PL intensity. Raman scattering shows the decrease of stress within the implanted films after thermal annealing. The carrier concentration increases monotonically with increasing annealing temperature up to 1100°C, which is in agreement with linewidth broadening of near band edge in PL spectrum. Moreover, systematic measurements implies that the implantation induced defects, especially point defects, which could play significant role in either the optical or electrical properties of films, cannot be completely annealed out at 1100°C.
Patent•
05 Nov 2003
TL;DR: In this paper, the activation rate of a semiconductor film is derived from the ratio of the obtained first dopant density to an added dopant densities, obtained from the SIMS analysis.
Abstract: PROBLEM TO BE SOLVED: To provide a new method for obtaining a dopant activation rate of a device, both accurately and easily, different from methods for obtaining a carrier density, using a hole measurement method and a CV measurement method, and to provide a method for manufacturing a device in which a proper threshold voltage control, that is, a dose control, has been performed, based on the obtained activation rate. SOLUTION: The activated dopant density (a first dopant density) of a semiconductor film is obtained from a threshold voltage and a flat band voltage of the device and a method for obtaining the dopant activation rate is derived from the ratio of the obtained first dopant density to an added dopant density (a second dopant density), obtained from the SIMS analysis. Thereby, the dopant activation rate in the channel formation region and the impurity region of the device can be obtained easily. COPYRIGHT: (C)2004,JPO&NCIPI
TL;DR: In this article, the N type Ni/SiC contact in the range of 175 K-450 K was measured for an applied drain to source voltage of 100 V and exhibits high power density capabilities of SiC VJFET as a controlled current limiter.
Abstract: Critical steps for the fabrication of SiC devices are thermal annealing and metal ohmic contact formation. Metal annealing effect on the electrical characteristics of the current limiter underlines the necessity to control this device fabrication step. Measurements of contact resistivity as a function of temperature demonstrate the stability of the N type Ni/SiC contact in the range of 175 K-450 K as its value remains constant around 40 µΩ.cm 2. Post implantation annealing effect on the sheet resistance (Rsh) shows that a 1700°C/30 min annealing gives better trade off in terms of dopant activation and surface roughness. High power density has been measured up to 600 V. Current thermal stability has been measured for an applied drain to source voltage of 100 V and exhibits high power density capabilities of SiC VJFET as a controlled current limiter. Introduction.
01 Jan 2003
TL;DR: In this paper, the dopant in the gate electrode was also activated during metal-induced crystal-lization (MIC) in polycrystalline silicon capacitors, and it was shown that there was an increase of about 0.1 eV in gate electrode workfunction due to Ni.
Abstract: We present a study of MOS capacitor reliability when nickel (Ni) is used to crystallize a phosphorus-doped, amorphous silicon ( -Si)-gate electrode by metal-induced crystal- lization (MIC). The dopant in the gate electrode was also activated during the MIC. We report that there was an increase of about 0.1 eV in the gate electrode workfunction due to Ni. Through capacitance-voltage (C-V), current-voltage (I-V) and charge-to- breakdown ( ) measurements, we show that the Ni MIC in the gate electrode does not degrade the MOS capacitor reliability. Index Terms—Capacitor reliability, dopant activation, metal-in- duced crystallization, polycrystalline silicon.
TL;DR: In this paper, the sheet resistance of poly-Si films was investigated using sheet resistance measurement and Raman measurement and it was shown that sheet resistance increases exponentially as the laser energy increases.
Abstract: The characteristics of dopant activation by sequential lateral solidification in poly-Si films is investigated using sheet resistance measurement and Raman measurement. Sheet resistance of n+ and p+ doped poly-Si films decreases exponentially as the laser energy increases. The minimum sheet resistance of n+ doped poly-Si films is 150 Ω/□ which is near to that of rapid thermal annealing (RTA) while the minimum sheet resistance of p+ doped poly-Si films is 180 Ω/□ which is less than a half to that of RTA. The sheet resistance of n+ and p+ doped poly-Si increases as the laser energy increases when the laser energy is above 573 mJ/cm 2 at which the nucleation occurs. Raman signal of n+ doped poly-Si films shows single peak at 515 cm -1 with all laser energy and has maximum intensity at 566 mJ/cm 2 laser energy. Raman signal of p+ doped poly-Si films shows single peak below 413 mJ/cm 2 laser energy and double peak above 444 mJ/cm 2 laser energy where the fully melting of p+ doped poly-Si film occurs.