Showing papers on "Dopant Activation published in 2010"

High performance germanium n-MOSFET with antimony dopant activation beyond 1×10 20 cm −3

Abstract: For the first time, high performance Ge nMOSFET is fabricated using laser annealing of ion-implanted antimony (Sb) dopants which provides donor activation beyond 1×1020cm−3 in germanium. Record I on /I off > 105 is demonstrated for n+/p junctions combined with significant reduction of contact resistance to 7×10−7 Ω-cm2. Performance projections for ITRS HP 22nm technology node are also discussed.

Probing the electrical properties of highly-doped Al:ZnO nanowire ensembles

Abstract: The analysis of transparent conducting oxide nanostructures suffers from a lack of high throughput yet quantitatively sensitive set of analytical techniques that can properly assess their electrical properties and serve both as characterization and diagnosis tools. This is addressed by applying a comprehensive set of characterization techniques to study the electrical properties of solution-grown Al-doped ZnO nanowires as a function of composition from 0 to 4 at. % Al:Zn. Carrier mobility and charge density extracted from sensitive optical absorption measurements are in agreement with those extracted from single-wire field-effect transistor devices. The mobility in undoped nanowires is 28 cm2/V s and decreases to ∼14 cm2/V s at the highest doping density, though the carrier density remains approximately constant (1020 cm−3) due to limited dopant activation or the creation of charge-compensating defects. Additionally, the local geometry of the Al dopant is studied by nuclear magnetic resonance, showing the...

Activation of Implanted n-Type Dopants in Ge Over the Active Concentration of 1 × 1020 cm − 3 Using Coimplantation of Sb and P

Abstract: One of the greatest challenges in fabricating a Ge-channel n-MOSFET is achieving a high n-type dopant activation within the source and drain regions. Conventional approaches to increase the electrically active doping level have been proven to be unsatisfactory, and typically the highest activation of n-type dopants is 4 × 10 19 cm -3 using phosphorus. This article describes a method to enhance the activation level of n-type dopants in Ge. Coimplantation of phosphorus and antimony leads to dopant activation over 1 X 10 20 cm -3 at 500°C. The enhancement of n-type dopant activation is attributed to reducing the implantation damage upon annealing due to increase in solid solubility of the dopants.

Activation of silicon wafer by excimer laser

Abstract: The application of lasers for annealing wafer-based and thin-film microelectronic devices is steadily increasing. Excellent control of material characteristics such as the dopant activation profile are achieved through proper selection of the laser parameters which directly influence the laser material interaction; these include wavelength, pulse duration and fluency. Nanosecond pulses at short UV wavelengths, as emitted by excimer lasers, are particularly beneficial for shallow activation and the increasing demand to keep the overall temperature budget low during the anneal. The short wavelength of e.g. 308nm or 248nm leads to an absorption depth of less than 10 nm in crystalline silicon that enables the deposition of the laser energy in a small confined volume. In this paper, we look at lasers, optics and annealing systems that have proved themselves in the annealing of semiconductor wafers. The application of a system for the uniform shallow activation of Back-Side-Illuminated (BSI) CMOS image sensors will be discussed in detail. This annealing system is based on a proven industrial excimer laser and yields a high uniformity of sheet resistance that is better than 0.5% (sigma). A unique optics system has been developed to provide a highly uniform thin line beam of 300 mm length. The wafer is covered in a single scan so that the process time for a 12″ wafer is reduced to only 20 seconds. Results from recent application work involving dopant activation for silicon wafers will also be presented.

Germanium $\hbox{n}^{+}/\hbox{p}$ Diodes: A Dilemma Between Shallow Junction Formation and Reverse Leakage Current Control

Abstract: This paper shows that germanium n+/p shallow junction formation often results in poor leakage current control. It is due to the counteraction between the fast diffusion of phosphorus and the high-temperature annealing requirement for dopant activation and defect annihilation. When the dopant concentration is above a threshold value, the concentration-dependent diffusion enhances phosphorus diffusion and results in a box profile, leading to an electrical concentration lower than its solid solubility limit. A refrained thermal budget may increase the active concentration, but it is not sufficient to repair the implantation-damaged lattice. Moreover, any plasma-involved fabrication processes after rapid thermal annealing may introduce additional field-assisted defects into the depletion region when the junction is near the surface. Thus, several tradeoffs must be considered between high P activation, low junction leakage, and a shallow junction in order to obtain functional negative-channel metal-insulator-semiconductor field-effect transistors.

Enhanced-Performance Germanium Nanowire Tunneling Field-Effect Transistors Using Flash-Assisted Rapid Thermal Process

Abstract: We report the enhanced performance of Ge nanowire (NW) tunneling field-effect transistors (TFETs), realized using a millisecond flash-assisted rapid thermal process (fRTP) for dopant activation. The electrical characteristics of our fRTP-activated NW TFETs exhibit maximum drive currents up toImax ~ 28 μA/μm at Vdd = -3 V and improved subthreshold swings. By comparison, NW TFETs realized using conventional RTP for dopant activation show an order of magnitude lower current. We attribute these findings to a more abrupt doping profile at the tunnel junction, owing to reduced dopant diffusion and improved dopant activation.

Low Temperature Germanium Growth on Silicon Oxide Using Boron Seed Layer and In Situ Dopant Activation

Abstract: Low temperature (<350°C) growth of germanium (Ge) on silicon dioxide (SiO 2 ) is demonstrated using a diborane pretreatment technique. Using SiH 4 and B 2 H 6 precursors, Si 1-x B x layers are deposited on Si0 2 to seed the chemical vapor deposition growth of Ge films. In the SiH 4 :B 2 H 6 system, the binary deposition mechanism of the Si 1-x B x film is explained by the "enhancement" model. In situ doping of Ge films is also investigated. In situ boron activation is achieved during the crystallization of the Ge films at 310°C. Device applicability of the doped Ge film growth on oxide is demonstrated in a low temperature (350°C) Si p-channel metal-oxide-semiconductor field-effect transistor, in which the Ge layer is used as a gate electrode. The low temperature Ge growth technique can be used for low thermal budget processes, e.g., monolithic three-dimensional integrated circuits.

Elastic strain and dopant activation in ion implanted strained Si nanowires

Abstract: Strained Si nanowires (NWs) are attractive for deeply-scaled complementary metal-oxide-semiconductor devices due to the combination of enhanced carrier mobility and excellent electrostatic control as was demonstrated with trigate metal-oxide-semiconductor field effect transistors. The challenge in using strained Si NWs for devices is to preserve the elastic strain during the required processing steps. In this work we investigated the influence of fundamental processing steps like patterning and dopant ion implantation on the structural and transport properties of strained Si layers and NWs on silicon-on-insulator (SOI) substrates. NWs with widths down to 35 nm, fabricated on 25 nm strained SOI and implanted to doses ranging from 5×1014 to 2×1015 ions/cm2 were investigated. We show that strain conservation and a low sheet resistivity of 6.2×10−4 Ω cm, close to the layer resistivity, can only be obtained if the NWs are patterned on doped layers. For NWs directly implanted to doses above 1×1015 ions/cm2, com...

Dopant and carrier profiling in FinFET-based devices with sub-nanometer resolution

Abstract: Atom probe tomography (APT) in conjunction with scanning spreading resistance microscopy (SSRM) is demonstrated for the first time to profile dopant and carrier distributions in FinFET-based devices with sub-nanometer resolution. These two techniques together provide information on the degree of conformality, the dose retention and the dopant activation. These results are also compared with a methodology involving secondary ion mass spectrometry (SIMS). Ion implantation for increased conformality of source/drain extensions is demonstrated for tilted implants, which clearly leads to improved device performance.

Nanoscale p-MOS Thin-Film Transistor With TiN Gate Electrode Fabricated by Low-Temperature Microwave Dopant Activation

Abstract: In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.

Investigating the surface quality and confinement of Si:P δ-layers at different growth temperatures

Abstract: We use scanning tunneling microscopy and low temperature magnetotransport measurements to study the effect of encapsulation temperature on phosphorus δ -layers in silicon. In particular we examine the quality of the resultant surface after encapsulation for the fabrication of three dimensional devices. Dopants were overgrown with 25 nm of silicon at temperatures between 250 and 300 °C. Electrical measurements show that 100% activation of dopants was obtained for 250 ∘ C encapsulation. However, dopant activation reduced to 54% as the growth temperature was increased to 300 ∘ C . Moreover we find that encapsulating above 270 ∘ C leads to dopant segregation that deactivates and broadens the δ -layer , without any substantial improvement in the quality of the regrowth surface.

Advanced techniques for achieving ultra-shallow junctions in future CMOS devices

Abstract: The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs, and new materials, such as high mobility substrates (Ge and/or III-V based). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under reduced thermal budget environments. While advanced dopant incorporation and activation techniques continue to be developed for Si scaling, implanting ions into III-V materials presents a fundamental problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. These challenges require the development of novel junction processing techniques that are inherently defect-free and can be controlled at the nm scale. One such promising technique, monolayer doping (MLD), is reviewed in this article.

Influence of Heating and Cooling Rates of Post-Implantation Annealing Process on Al-Implanted 4H-SiC Epitaxial Samples

Abstract: We report on topographical, structural and electrical measurements of aluminum-implanted and annealed 4H-SiC epitaxial samples. The influence of heating-up and cooling-down temperature rates on the SiC surface roughness, the crystal volume reordering and the dopant electrical activation was particularly studied. A higher heating-rate was found to preserve the rms roughness for annealing temperatures lower than 1700°C, and to improve the sheet resistance whatever the annealing temperature due to a better dopant activation (except for 1600°C process, which induced a dark zone in the sample volume). A complete activation was calculated for an annealing at 1700°C during 30 minutes, with a ramp-up at 20°C/s. Rising the cooling-down rate appeared to increase the sheet resistance, probably due to a higher concentration of point defects in the implanted layer.

Photoreflectance characterization of ultrashallow junction activation in millisecond annealing

Abstract: Photoreflectance (PR) provides an optical means for rapid and precise measurement of near-surface electric fields in semiconductor materials. This article details the use of PR to characterize dopant activation in ultrashallow junction (USJ) structures formed using millisecond annealing processes. USJ structures were formed in silicon using 500eV B implantation with a dose of 1015∕cm2, followed by flash anneals at 1250–1350°C. Reference metrology was performed using secondary ion mass spectrometry and various sheet resistance (Rs) methods. Methods to calibrate PR signals to active carrier concentration in USJ structures, including halo-doped samples, are described. PR is shown to be highly sensitive to active dopant concentrations in USJ structures formed by millisecond annealing.

Activation of B and As in Ultrashallow Junction During Millisecond Annealing Induced by Thermal Plasma Jet Irradiation

Abstract: We have investigated effects of annealing temperature and heating and cooling rates during millisecond annealing on the activation of B and As in the Si lattice. In the case of As+-implanted samples, efficient dopant activation was observed at a temperature higher than 1000 K, while it was observed at a temperature higher than 1400 K in the case of B-implanted samples. The sheet resistance (RS) of B-implanted samples monotonically decreases with temperature, and no significant dependence on heating rate (Rh) or cooling rate (Rc) is observed. On the other hand, As+-implanted samples show significant dependence of RS on Rh and Rc. We have performed thermal plasma jet (TPJ) annealing on an As2+-implanted sample, and obtained an ultrashallow junction (USJ) with a junction depth (Xj) of 11.9 nm and a RS of 1095 Ω/sq. B USJ is also obtained with a Xj of 23.5 nm and a RS of 392 Ω/sq. Precise control of Rh and Rc in addition to annealing temperature is quite important for achieving highly efficient doping in USJ.

Method and apparatus for controlled thermal processing

Abstract: A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal measurement device positioned to measure temperature on a second area of the material being processed, the first device being relatively more sensitive to changes in surface emissivity than the second device. By comparing the outputs of the two devices, emissivity changes can be detected and used as a proxy for some physical change in the workpiece and thereby determine when the desired process has been completed. The system may be used to develop a process recipe, or it may be part of a system for real-time process control based on emissivity changes. Applicable processes include heating, annealing, dopant activation, silicide formation, carburization, nitridation, sintering, oxidation, vapor deposition, metallization, and plating.

Millisecond anneal for ultra-shallow junction applications

Abstract: As CMOS devices are scaled down, dopant activation, junction profile control and silicide engineering become increasingly important. To address these ultra-shallow junction (USJ) challenges, millisecond anneal (MSA) has emerged as a main stream thermal process technology for advanced CMOS device fabrication. In this paper, we will discuss two major classes of applications for MSA in USJ: achieving effective dopant activation with limited diffusion and to facilitate Ni-based silicidation with reduced leakage. Some issues and process solutions to address them will also be examined.

Flexibly-Shaped-Pulse flash lamp annealing with assisted temperature control (FSP-FLA plus ) to realize a wide range of annealing conditions

Abstract: Millisecond annealing (MSA), such as flash lamp annealing (FLA) and laser spike annealing, is used for dopant activation of ultra-shallow junctions (USJ) in scaled complimentary metal-oxide-semiconductor (CMOS) devices. This is because lower sheet resistance (Rs) and less dopant diffusion are achieved with MSA and these are crucial requirements for minimizing the junction depth (Xj) in state-of-the-art CMOS [1–5]. In FLA the sample is irradiated for a few milliseconds with a Xe-lamp after pre-heating to 500°C or more. The assisted heating is done either using a resistive heater or by irradiation with a halogen lamp. With lamp heating, the assisted temperature (T A ) range is from 500 to 1000°C compared with from 300 to 600°C using a resistive heater. In addition, with lamp assisted heating the temperature profile can be controlled to the second order, similar to spike rapid thermal annealing (sRTA). Thus, we can use higher T A with less dopant diffusion, and higher pre-heat temperatures enable higher peak temperatures during Xe-lamp irradiation. We also used a Flexibly-Shaped-Pulse (FSP) system to control the annealing time and temperature [6–10]. By combining FSP technology with lamp assisted heating, we expect to be able to have control over a wide-range of annealing times and temperatures. In addition, this combination may produce a synergistic effect on device performance. In this report, we examine, first, the effects of high assisted temperatures. Then, we demonstrate the excellent potential of combining FSP technology and lamp assisted heating on device performance.

Low temperature dopant activation using variable frequency microwave annealing

Abstract: Variable frequency microwaves (VFM) and rapid thermal annealing (RTA) were used to activate ion implanted dopants and re-grow implant-damaged silicon. Four-point-probe measurements were used to determine the extent of dopant activation and revealed comparable resistivities for 30 seconds of RTA annealing at 900 °C and 6-9 minutes of VFM annealing at 540 °C. Ion channeling analysis spectra revealed that microwave heating removes the Si damage that results from arsenic ion implantation to an extent comparable to RTA. Cross-section transmission electron microscopy demonstrates that the silicon lattice regains nearly all of its crystallinity after microwave processing of arsenic implanted silicon. Secondary ion mass spectroscopy reveals limited diffusion of dopants in VFM processed samples when compared to rapid thermal annealing. Our results establish that VFM is an effective means of low-temperature dopant activation in ion-implanted Si.

22nm node p+ USJ defect analysis with various PAI and HALO structures using laser annealing

Abstract: Boron 200eV 1E15/cm2 p+ Ultra Shallow Junctions with various PAI (Ge, Xe & In) and HALO (As & Sb) implantation activated by msec laser annealing (1220°C to 1350°C) were studied using Junction Photo Voltage (JPV) and Modulated Photo Reflectance (MPR). JPV and MPR provided information about junction quality; dopant activation, junction capacitance, residual implant damage and junction leakage. Highest p+ junction quality and best p+ dopant activation was achieved with laser annealing temperatures >1300°C. The results with Sb-HALO were worse than with As-HALO. For HALO implants junction leakage was controlled by direct band to band tunneling while for no HALO it was controlled by end of range residual PAI defects. The high junction leakage (exceeding E-5 A/cm2) could lead to unreliable Rs and junction capacitance determination.

Pulsed laser annealing technology for nanoscale fabrication of silicon-based devices in semiconductors

Abstract: This chapter reviews and summarizes recent advances in laser-induced formation of ultrashallow p+-doped junctions and silicide using single- and multiple-pulsed laser annealing. Pulsed laser annealing is a transient annealing which facilitates very fast melting, mixing, and quenching. It can be used to control dopant diffusion by induced melt depth. Therefore an extremely high degree of dopant activation and defect annealing are achieved upon recrystallization. It is also possible to tailor the composition, structural, and interface characteristics of the resultant silicide layer by varying the laser fluence and number of pulses, which makes it versatile for applications.

Ultra shallow junctions with high dopant activation and GeO 2 interfacial layer for gate dielectric in germanium MOSFETs

Abstract: For the first time, ultra shallow junctions (x j 1×1020 cm−3) is achieved for all dopant atoms (P/As/Sb/B) using Laser Thermal Processing. We also show ultrathin (0.6nm), high quality GeO 2 interfacial layer for gate dielectric, which provides substrate orientation independent D it and mobility enhancement for Ge high-k N/P MOSFETs.

Characterization of dopant activation, mobility and diffusion in advanced millisecond laser spike annealing

Abstract: Recently we reported the development of new dual beam laser spike annealing system that offers flexible temperature profiles and a broad range of process parameters. For example, the dwell time can be varied from a few hundred microseconds to several tens of milliseconds, while simultaneously allowing the substrate temperature to be lowered significantly to accommodate silicide processes. Short anneal times are generally required to achieve the best R S -X j for junction scaling and reduction of strain relaxation, while longer anneal times provide for controlled impurity diffusion and the potentially enhanced defect annealing. In this paper, we present data from a systematic study of the role of dwell and peak temperature on annealing properties of electrically active impurities. Carrier activation and mobility data were obtained by Hall measurements and dopant profiles from SIMS. Thermal activation energies are extracted from these data covering temperatures in the 1100–1300°C range and over dwell times of 0.4ms to 20 ms.