Showing papers on "Electronic design automation published in 1990"

OPASYN: a compiler for CMOS operational amplifiers

Abstract: A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and (3) mask geometry construction using a macro cell layout style. The synthesis process is fast enough for the program to be used interactively at the system design level by system designers who are inexperienced in operational amplifier design. >

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

Abstract: The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block. >

Probabilistic simulation for reliability analysis of CMOS VLSI circuits

Abstract: A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST (current estimator) which has shown excellent accuracy and dramatic speedups compared with traditional approaches. The approach and its implementation are described, and the results of numerous CREST runs on real circuits are presented. >

A literature survey of fixture- design automation

Abstract: This paper gives a review of fixture-design research, most of it done in the 1980s. The major topics of the review are the fixturing prbwiples (supporting, locating and clamping), automated fixture design (configuration, assembh' and verification), and fixture hardware design (dedicated. modular and electric/ magnetic types).

Constraint generation for routing analog circuits

Abstract: An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits. >

Data path tradeoffs using MABAL

Abstract: This paper describes a set of novel tradeoff experiments using MABAL, a Module And Bus ALlocation program. MABAL uses a simple heuristic algorithm to concurrently perform functional unit allocation, register allocation, interconnect allocation and module binding, while minimising overall cost. MABAL was used to produce over 3000 RTL designs from a specification which had been previously scheduled. Tradeoffs between buses and multiplexers and between data steering logic and functional logic were investigated. The results indicate data path tradeoffs are sensitive to the characteristics of the module library used, and illustrate the difficulty of integrating module generation or logic synthesis with high-level synthesis. This tradeoff study has also highlighted MABAL's capabilities and is unlike any other reported in the literature.

Application of nonlinear design optimization for power converter components

Abstract: A computer-aided-design approach for power converter components is described. A designer with a minimum of programming and optimization experience can interface with nonlinear optimization routines to rapidly perform design trade-offs that would be impossible by hand. A power converter design using MOSFET and bipolar-junction-transistor (BJT) switches is shown to illustrate the power of optimization routines in power electronics. Realistic design values and available vendor components can be incorporated in a design without using an extensive database program structure. A practical example is given with experimental data to verify the accuracy and usefulness of optimization software. >

Logic-based approach for modeling organization of design standards

Abstract: Several studies have been conducted on representing and processing design standards for design automation. One of the main outcomes of these studies is the standards analysis, synthesis, and expression (SASE) model. To extend the utility of the SASE model for processing (reasoning about) design standards, a logic‐based approach is proposed. This approach provides: (1) A formal language, founded on predicate logic, for representing the standard; and (2) a mechanical means for reasoning about the standard using the language. The formal language is used to model the overall organization of a portion of the American Institute of Steel Construction (AISC) design specification. The model, called the formal organizational submodel, is composed of a set of axioms that capture the relationships between the classifiers and the provisions of the standard. Reasoning about the formal organizational submodel is accomplished using the resolution theorem proving strategy. This paper's main contribution is its use of pred...

On the architecture of a CAD framework: The NELSIS approach

Abstract: In this paper we present the principles of the architecture of a CAD framework that puts a substantial added-value under the fingertips of the designer by organizing the design information and keeping track of the design evolution, and in addition permits integration of tools of different origin and achieves run-time efficiency.We provide a rationale for partitioning the design information into raw data and meta data, then we model the meta data and define the architecture of the framework. Key features of this framework are its high level services for tool integration and extensive browsing facilities for the designer. The principles presented have been implemented in the Nelsis IC Design System in which they have proven their usefulness and efficiency.

An object-oriented VHDL design environment

Abstract: A system-level design environment (SDE) for the VHSIC hardware description language (VHDL) is presented. The object-oriented approach is used for modeling the VHDL entities, design constraints, and even design patterns. The data model and its internal schema, which are suitable for the VHDL semantics, are proposed. SDE allows a designer to reconfigure the designed schematic by binding its generic components to technology-specific ones. It is effectively used for version control. SDE verifies the design by dynamically checking the constraints. The standard VHDL is extended in order to represent the constraints properly. >

A global delay model for domino CMOS circuits with application to transistor sizing

Abstract: Domino CMOS circuits have played important roles in the design of high-speed VLSI chips such as 32-bit microprocessors and their family chips. Many researchers have worked on the characterization of the delay time and optimal design of domino CMOS circuits using circuit simulators as the main CAD tools. This paper presents a global analytical delay model for an important class of domino CMOS circuits wherein a multitude of n-channel transistors form a series connection. the new model is shown to predict the delay time from the precharging clock edge to the 0.5 VDD output level with less than 10% error as compared to that from SPICE simulation over the entire design space. the delay model has been applied efficiently to the design automation of domino CMOS circuits modules.

Design for test using partial parallel scan

Abstract: Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the drawback that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. A scan design technique termed partial parallel scan which reduces test application effort by one to two orders of magnitude is presented. Theoretical and practical aspects of the design method are discussed. The practical use of the partial parallel scan technique has been demonstrated with an LSI circuit and a VLSI circuit designed using silicon compiler tools. >

Applications '90: design tools

Abstract: Developments in design tools over the past year are examined. Progress was more incremental than in the past, consisting of refinement rather than innovation. Logic synthesis gained acceptance, while behavioral-level synthesis moved a step closer to reality. Testability became a design parameter, hardware accelerators got even faster, and work continued on developing frameworks that will allow one tool to retrieve information from another and display it in a uniform manner. >

Design methodology management-a CAD framework initiative perspective

Abstract: The design of today's electronic systems involves the use of a growing number of complex CAD tools. Invoking and controlling these tools, independently or as part of a captured, multi-operation flow, remains an error-prone and largely unsolved problem. This problem is the focus of the Design Methodology Management Technical Subcommittee (DMMTSC) of the CAD Framework Initiative. This paper describes the DMM problem, establishes DMM requirements, and presents the state of the DMMTSC effort to define interface standards for proposed solutions.

Empirical failure analysis and validation of fault models in CMOS VLSI

Abstract: A methodology for the experimental evaluation of fault models, using fault diagnosis as the basic approach, is developed. The methodology includes a way of determining the defect level of test sets, in addition to determining the adequacy of the fault models used to generate them. The key elements of the method are the design and fabrication of an easily diagnosable test chip, representative of the class of circuits being studied, the CAD (computer-aided-design) tools used in its design, and its fabrication process; the derivation of an extremely robust test set, capable of detecting faults from within a wide range of fault models; the development of a set of diagnostic tools to perform automated diagnosis on faulty circuits and the use of the results to get measures of 'effectiveness' of the fault models considered; the validation of the results of the diagnosis by means of an electron-beam voltage-contrast circuit prober. Experimental results from a large number of samples of the test circuit are presented. >

ISAID-a methodology for automated analog IC design

Abstract: A methodology called ISAID for the automated generation of analog integrated circuit designs is presented. The methodology makes use of a hierarchical design procedure to break down the required system specifications into transistor descriptions. The methodology provides a correction procedure which enables designs which fail to meet the required specifications when simulated or laid out to be corrected either by altering circuit component sizes or by making changes in the designed topology itself. Some approaches to analog IC design are briefly reviewed. A two-stage operational amplifier design example is presented. >

An intelligent design system for analogue integrated circuits

Abstract: A new design methodology for the design of arbitrary analogue functional blocks (op amps, comparators . . .) is presented. The method combines symbolic simulation, numerical optimization and knowledge-based techniques and covers the whole design path from analytic modeling over optimal circuit sizing down to layout. This path is repeatedly passed through on different hierarchical levels for higher-level blocks. The main advantage of the new CAD system is that it is not limited to a fixed set of circuit topologies. It can automatically design any new circuit by the introduction of artificial intelligence techniques: building block recognition, design equation manipulation, self-learning capabilities. . . These features make it an intelligent and flexible analogue design system. >

Databases and cell-selection algorithms for VLSI cell libraries

Abstract: The issues that must be addressed before commercial database management systems can be used to manage VLSI CAD data are defined. A survey is presented of approaches addressing four of the defined issues: design hierarchies and multilevel representations, design alternatives and version control, common interface between cell libraries and efficient cell selection based on given design constraints. A frame-based model is considered as a case study of the special-purpose design database management system approach. This framework for capturing design data is based on semantic networks. It is well suited for application-specific ICs, yet general enough for other CAD/CAM environments. Benchmark results for the selection algorithms that run on top of the frame-based database system are presented. >

A design platform for the NELSIS CAD framework

Abstract: A design platform is a central user interface to a CAD framework. It enables information retrieval, object selection, and tool activation in a uniform and integrated fashion. A description is given of such a design platform with emphasis on the graphical metadesign data-browsing facilities. The design platform informs designers about the latest developments of their designs and simplifies interaction with the design system. It enables designers to concentrate more on their main task of electronics design, resulting in better designs and increased productivity. Although the design platform presented has been implemented on top of the NELSIS CAD framework, the ideas and concepts can be used in a variety of applications where data of interest to end users are maintained by a framework. >

PRIDE: An Integrated Design Environment for Semiconductor Device Simulation

Abstract: Philips Research Integrated Device Environment (PRIDE) is a computer-aided design (CAD) system for the rapid specification and evaluation of semiconductor devices. Using a windows icons menus pointer (WIMP) based graphical user interface, the environment incorporates a diverse set of semiconductor device simulation programs into one integrated, extensible CAD framework. This framework provides a uniform interface for the engineer interested in device simulation. PRIDE is composed of three independent modules: (i) picasso, a graphical preprocessor used to input the geometry and doping profiles of a device, (ii) various simulation programs in which the semiconductor device equations are solved numerically, and (iii) prism, an interactive color graphics post-processor for the rapid display and analysis of solution results. >

The ADAM analog design automation system

Abstract: An open analog design system is presented that can generate layouts of analog cells and subsystems starting from desired functional specifications and a technology description which can be CMOS, bipolar, or BICMOS The design system includes model parameter verification, symbolic analysis, design, optimization, and automatic documentation of cells The schematics of the analog cells can be selected out of a library or can be entered by the designer Either a full description of the schematic is given or a new schematic is composed starting from a library of subblocks The layout generator, which is process portable, handles typical analog layout constraints during placement and routing All tools can be used in a full automatic mode or can be used interactively to allow more experienced designers to impose their point of view >

Towards mixed analog/digital design automation: a review

Abstract: The state of the art in design automation for analog and mixed analog-digital circuits is reviewed. Emphasis is given to the areas of physical assembly, synthesis, and silicon compilation. Several notable aspects of the problem, such as mixed mode or multilevel simulation, modeling, and testability, albeit important, are beyond the scope of this paper and are not reviewed. The approaches are examined separately for the cases of analog circuits and mixed signal circuits. For each of these categories, the CAD tools are discussed first, followed by synthesis and compilation activities. >

Hierarchical test assembly for macro based VLSI design

Abstract: A novel incremental procedure for the hierarchical assembly of macro test specifications into a chip test program is presented. To solve test generation/application problems, a bottom-up symbolic test assembly procedure that proceeds in line with the construction of the system is proposed. It is shown that for a modular design approach, this procedure can be extended with design-for-testability features to ensure that all macro tests are assembled into a chip test program. The approach is exemplified by the design of a decimation filter for a Sigma / Delta A/D (analog-to-digital) converter. >

A prototype system for design automation via the browsing paradigm

Abstract: Design activity is often characterized by a search in which the designer examines various alternatives at several stages during the design process. Current computer-aided design (CAD) systems, however, provide very little support for this exploratory aspect of design. Two major problems exist: rapid generation of design alternatives, and presentation of these alternatives to the user in an accessible manner. This paper provides the foundations for a novel CAD technology intended to encourage a synergistic, cooperative relationship between the computer and the human designer: at any stage in the design process, the user can request that the system generate automatically design alternatives that satisfy certain constraints. These alternatives are structured by the system in a spatial framework using properties specified by the user as independent dimensions. The user can systematically brow&e through the design alternatives via graphical gestures such as scrolling and pointing, and select any of these designs for further development. A prototype CAD system-FLATS-supporting this cooperative design paradigm has been constructed; it consists of three major modules : the modeling &y&tem, the grammar.directed con&trained generator, and the brow&ing system. This paper describes the algorithms and data representations used by these modules, and demonstrates the use of the system to design small architectural floor plans . A videotape demonstrating the prototype system accompanies this paper. K eywords: Graphical user interfaces, spatial data management, direct manipulation, design automation, human factors, human-machine interaction, constraint-based design, grammar-directed design.

Artificial intelligence and design

Abstract: Developments in computer science, especially in artificial intelligence (AI) and related areas of advanced computing, provide a unique opportunity to push beyond the present level of computer-aided automation technology and attain substantial advances in the understanding and mechanization of design processes. The general nature of design problems and the scientific issues involved in studying them with the help of AI approaches are discussed. A number of research problems that need special attention are identified. Examples of current AI work on specific design tasks are presented. New research directions are discussed in the context of new design tasks of increased complexity where domain knowledge is largely intractable. >

Layout compaction with attractive and repulsive constraints

Abstract: A one-dimensional compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks[expands] the spaces among the specified layout elements without causing any design rule violations, as if some force were affecting them. It implies that the resultant layout has less cross talk and delay. The proposed network simplex algorithm experimentally proves to be efficient in both time and space.

Simulator Evaluation of the Final Approach Spacing Tool

Abstract: This paper describes the design and simulator evaluation of an automation tool for assisting terminal radar approach controllers in sequencing and spacing traffic onto the final approach course. The automation tool, referred to as the Final Approach Spacing Tool (FAST), displays speed and heading advisories for arrivals as well as sequencing information on the controller's radar display. The main functional elements of FAST are a scheduler that schedules and sequences the traffic, a 4D trajectory synthesizer that generates the advisories, and a graphical interface that displays the information to the controller. FAST has been implemented on a high performance workstation. It can be operated standalone in the Terminal Radar Approach Control (TRACON) Facility or as an element of a system integrated with automation tools in the Air Route Traffic Control Center (ARTCC). FAST was evaluated by experienced TRACON controllers in a realtime air traffic control simulaton. Simulation results summarized in the paper show that FAST significantly reduced controller workload and demonstrated a potential for an increase in landing rate.

A practical online design rule checking system

Abstract: In this paper, we propose a practical online design rule checking system, which can provide the following features: an ability to cope with a complicated and wide variety of design rules with high accuracy, easy use, high speed incremental DRC (simultaneous checking with pattern editing) and total DRC (non-simultaneous checking), high speed pattern editing, and a small memory space. For the last three items, a field block data structure is developed. Experimental results show this system is very effective for VLSI cell layout design.

Synthesis of analog circuits using a blackboard approach

Abstract: A novel approach to the design automation of analog circuits is presented. The prototype implementation -OASE- has been realized as a set of cooperating expert systems with blackboard architectures. The circuit specific knowledge bases use hybrid representation schemes and are strictly separated from the execution engine. This alleviates the knowledge acquisition process as well as the extension and maintenance of existing knowledge. OASE has been developed as a design assistant, providing a hierarchical design style and fully embedded standard algorithmic tools.

FIRGEN: a CAD system for automatic layout generation of high-performance FIR filter

Abstract: A novel functional compiler, FIRGEN, for automatic generation of finite-impulse response (FIR) filters using custom and gate-array technologies is described. It consists of CAD tools to automate the entire design from filter specifications to final chip layout. The architecture and floorplan description generation by FIRGEN can be used to drive custom macrocell or gate-array place and route tools to generate the final layout. A unique feature of the compiler is that it uses architecture and floorplanning techniques that are targeted at FIR filters with sample rates in the region 10-100 MHz for video and digital communication applications. Results of three chips designed with FIRGEN are presented. >